[PATCH] clk: eswin: Keep the TCU AXI clock enabled

[Xuyang Dong]

> 
> The SMMU TCU needs its AXI clock for DMA, even in bypass mode. No driver
> claims this clock, so clk_disable_unused() gates it and DMA through the
> SMMU stalls. On the HiFive Premier P550, this hangs firmware loading of
> an RX550 graphics card.
> 
> Mark the clock as critical.
> 
> Fixes: cd44f127c1d4 ("clk: eswin: Add eic7700 clock driver")
> Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
> ---
> Tested on the HiFive Premier P550 with an RX550 graphics card:
> 
> - Without this patch, amdgpu stalls while loading the RX550 firmware
>   and CPUs can no longer be halted.
> - With only the TCU AXI clock kept enabled (the TCU configuration clock
>   is still managed normally), amdgpu initializes and the IB ring tests
>   pass without any manual register writes.
> ---
>  drivers/clk/eswin/clk-eic7700.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/eswin/clk-eic7700.c b/drivers/clk/eswin/clk-eic7700.c
> index 43a47fe16ab14ae1d1cacc3a0da0203e412541c0..7c95055f13eb782a03723e4475d63060d37711aa 100644
> --- a/drivers/clk/eswin/clk-eic7700.c
> +++ b/drivers/clk/eswin/clk-eic7700.c
> @@ -832,8 +832,10 @@ static struct eswin_clk_info eic7700_clks[] = {
>  	ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk",
>  			EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
>  			CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0),
> +	/* DMA through the SMMU still needs the TCU AXI clock in bypass mode. */
>  	ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk",
> -			EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT,
> +			EIC7700_CLK_DIV_DDR_ACLK_DYNM,
> +			CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>  			EIC7700_REG_OFFSET_TCU_ACLK, 31, 0),
>  	ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk",
>  			EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE,
> 

Acked-by: Xuyang Dong <dongxuyang at eswincomputing.com>

Thanks,
Xuyang Dong