[PATCH v2] spi: sifive: clamp the clock divider to the register range

[Mark Brown]

On Tue, Nov 10, 2026 at 10:57:41PM +0800, shao.mingyin at zte.com.cn wrote:
> From: Shao Mingyin <shao.mingyin at zte.com.cn>
> 
> sifive_spi_prep_transfer() divides by t->speed_hz, which can remain
> zero when neither the device nor the controller provides a maximum
> speed. For a nonzero but very low speed, masking the divider to 12 bits
> can also wrap it to a small value and program a much faster clock.

This was previously part of a series of five patches, I see you've
resent two of them as independent patches when I was expecting the
standard workflow which would be to revise the series.  This makes
things difficult to track, I'd discarded the old version waiting for the
new one.
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