[PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells

[Aurelien Jarno]

Hi,

On 2026-11-06 14:05, Jiayu Du wrote:
> Add the K3 eFuse controller with its AES_WTM clock and reset. Describe
> fixed-layout cells for the temperature calibration parameters stored in
> bank 0 and bank 7, using controller-relative offsets.
> 
> Leave the controller disabled for board-level enablement.

What is the reason for enabling it at the board-level? AFAIU, this is 
part of the SoC and does not require any board level hardware. Therefore 
I believe it should just be enabled by default.

> Signed-off-by: Jiayu Du <duge1256 at gmail.com>
> ---
>  arch/riscv/boot/dts/spacemit/k3.dtsi | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index e89d2cc5ca8c..51861fdc6a21 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -1439,6 +1439,31 @@ saplic: interrupt-controller at e0804000 {
>  
>  		/* sec_i2c3: 0xf0614000, not available from Linux */
>  
> +		efuse: efuse at f0702800 {
> +			compatible = "spacemit,k3-efuse";
> +			reg = <0x0 0xf0702800 0x0 0x400>;
> +			clocks = <&syscon_apmu CLK_APMU_AES_WTM>;
> +			resets = <&syscon_apmu RESET_APMU_AES_WTM>;
> +
> +			status = "disabled";
> +
> +			nvmem-layout {
> +				compatible = "fixed-layout";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +
> +				soc_rtemp_trim1: temperature-trim at 120 {
> +					reg = <0x120 0x1>;
> +					bits = <0 8>;
> +				};
> +
> +				soc_rtemp_trim: temperature-trim at 19a {
> +					reg = <0x19a 0x2>;
> +					bits = <4 8>;
> +				};

I have tried this patchset, and while I can see non-zero data in the 
/sys/bus/nvmem/devices/f0702800.efuse, both temperature calibration data 
appear as 0. Is that expected?

Regards
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien at aurel32.net                     http://aurel32.net