[PATCH 1/3] dt-bindings: rtc: Add StarFive JH7110 RTC

[Conor Dooley]

On Fri, Nov 06, 2026 at 05:55:58PM +0000, Owen O'Hehir wrote:
> Describe the RTC in the always-on domain of the StarFive JH7110 SoC.
> 
> Signed-off-by: Owen O'Hehir <oo.hehir at gmail.com>
> ---
>  .../bindings/rtc/starfive,jh7110-rtc.yaml     | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml b/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml
> new file mode 100644
> index 000000000..95edddea1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/starfive,jh7110-rtc.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/starfive,jh7110-rtc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Real Time Clock
> +
> +maintainers:
> +  - Alexandre Belloni <alexandre.belloni at bootlin.com>

Really, this should be you or someone that actually cares about the rtc
on this device, not the subsystem maintainer.
pw-bot: changes-requested

Otherwise, this looks fine.

Cheers,
Conor.


> +
> +description:
> +  The RTC in the always-on domain of the StarFive JH7110 SoC. It counts BCD
> +  time and date from a 32.768 kHz clock and has an alarm, a frequency offset
> +  adjustment and millisecond and one-second pulse outputs.
> +
> +allOf:
> +  - $ref: rtc.yaml#
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-rtc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: Millisecond pulse
> +      - description: One-second pulse
> +      - description: Alarm and calibration events
> +
> +  interrupt-names:
> +    items:
> +      - const: ms-pulse
> +      - const: sec-pulse
> +      - const: rtc
> +
> +  clocks:
> +    items:
> +      - description: APB bus clock
> +      - description: Calibration reference clock
> +      - description: 32.768 kHz counter clock
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: cal
> +      - const: 32k
> +
> +  resets:
> +    items:
> +      - description: 32.768 kHz counter domain reset
> +      - description: APB bus reset
> +      - description: Calibration reset
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - resets
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +    rtc at 17040000 {
> +        compatible = "starfive,jh7110-rtc";
> +        reg = <0x17040000 0x10000>;
> +        interrupts = <10>, <11>, <12>;
> +        interrupt-names = "ms-pulse", "sec-pulse", "rtc";
> +        clocks = <&aoncrg JH7110_AONCLK_RTC_APB>,
> +                 <&aoncrg JH7110_AONCLK_RTC_CAL>,
> +                 <&aoncrg JH7110_AONCLK_RTC_32K>;
> +        clock-names = "apb", "cal", "32k";
> +        resets = <&aoncrg JH7110_AONRST_RTC_32K>,
> +                 <&aoncrg JH7110_AONRST_RTC_APB>,
> +                 <&aoncrg JH7110_AONRST_RTC_CAL>;
> +    };
> -- 
> 2.43.0
> 
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