[PATCH v6 0/5] Add workarounds for Picoheart errata

[Yicong Yang]

This series adds an errata framework for Picoheart SoCs and workarounds
for two hardware issues: unreliable cbo.clean writeback and unavailable
AMOCAS.Q despite the Zacas extension being advertised.

On affected CPUs, use cbo.flush for kernel cache writeback and trap
userspace cbo.clean/cbo.flush instructions to emulate them with cbo.flush.
Disable kernel cmpxchg128 support while retaining the other Zacas
operations. The supporting patches share the instruction-fetching helper
between fault handlers, add MXR support for execute-only mappings, and
add CBO instruction decoding definitions.

[Apply Notice]
Patch 1/5 based on below fix of stale SR_* on context switch.
https://lore.kernel.org/all/20261022083212.84721-1-cuiyunhui@bytedance.com/

Changes since v5:
- Rebase on v7.4-rc1 and drop the obsolete RISCV_ALTERNATIVE stuffs
- Use the simpler v4-style get_user() wrapper in __read_insn()
- Add Tested-by tags from Han Gao. Thanks for testing.
Link: https://lore.kernel.org/linux-riscv/20261017083100.40157-1-yang.yicong@picoheart.com/

Changes since v4:
- Rebase on v7.3-rc7.
- Make the CBO erratum depend on MMU.
- Limit MXR enablement to __get_user().
- Restrict Picoheart errata to 64BIT and skip alternative patching during
  RISCV_ALTERNATIVES_EARLY_BOOT.
Link: https://lore.kernel.org/linux-riscv/20260915083305.81913-1-yang.yicong@picoheart.com/

Changes since v3:
- Work around AMOCAS.Q by patching system_has_cmpxchg128().
Link: https://lore.kernel.org/linux-riscv/20260907072149.72031-1-yang.yicong@picoheart.com/

Changes since v2:
- Rebase on v7.3-rc2.
- Merge the MXR fix and get_insn() extraction into one patch.
Link: https://lore.kernel.org/linux-riscv/20260728094627.94975-1-yang.yicong@picoheart.com/

Changes since v1:
- Factor out a common get_insn() for reading userspace instructions.
- Fix instruction fetching from execute-only mappings.
- Apply cleanups and coding-style refinements from review.
Link: https://lore.kernel.org/linux-riscv/20260715084724.26578-1-yang.yicong@picoheart.com/

Yicong Yang (5):
  riscv: Make get_insn public for instruction fault handling
  riscv: insn: Support decoding of CBO instructions
  riscv: errata: Add init framework for picoheart errata
  riscv: errata: picoheart: Add workaround for cbo.clean errata
  riscv: errata: picoheart: Add workaround for AMOCASQ errata

 arch/riscv/Kconfig.errata                    |  35 +++
 arch/riscv/errata/Makefile                   |   1 +
 arch/riscv/errata/picoheart/Makefile         |   5 +
 arch/riscv/errata/picoheart/errata.c         | 235 +++++++++++++++++++
 arch/riscv/include/asm/alternative.h         |   3 +
 arch/riscv/include/asm/cmpxchg.h             |  18 +-
 arch/riscv/include/asm/csr.h                 |   1 +
 arch/riscv/include/asm/errata_list.h         |  25 +-
 arch/riscv/include/asm/errata_list_vendors.h |   5 +
 arch/riscv/include/asm/insn.h                |  63 ++++-
 arch/riscv/include/asm/processor.h           |   2 +-
 arch/riscv/include/asm/vendorid_list.h       |   1 +
 arch/riscv/kernel/alternative.c              |   5 +
 arch/riscv/kernel/asm-offsets.c              |   6 +-
 arch/riscv/kernel/cpufeature.c               |   3 +
 arch/riscv/kernel/entry.S                    |  14 +-
 arch/riscv/kernel/traps.c                    |   4 +
 arch/riscv/kernel/traps_misaligned.c         |  52 ----
 arch/riscv/kernel/vector.c                   |   6 +-
 19 files changed, 414 insertions(+), 70 deletions(-)
 create mode 100644 arch/riscv/errata/picoheart/Makefile
 create mode 100644 arch/riscv/errata/picoheart/errata.c

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2.54.0 (Apple Git-157)