[PATCH v3 1/2] riscv: build kernel atomics from LR/SC when Zaamo is disabled

[Conor Dooley]

On Tue, Nov 03, 2026 at 02:57:29PM +0200, Vladimir Kondratiev wrote:
> Some of issues already fixed on v4.
> - Link to v4:
> https://patch.msgid.link/20261101-lrsc-only-v4-0-4e1d010463b3@mobileye.com
> 
> On 11/2/26 20:46, Conor Dooley wrote:
> > On Mon, Oct 26, 2026 at 11:20:02AM +0200, Vladimir Kondratiev wrote:
> >> The A extension is Zaamo plus Zalrsc. MIPS P8700 implements only
> >> Zalrsc, and its AMO instructions trap to SBI. A typical atomic is
> >> about 40 cycles with LR/SC and about 600 cycles with an emulated AMO,
> >> so keep the existing AMO sequences when the toolchain defines
> >> __riscv_zaamo or __riscv_atomic, and use an LR/SC loop otherwise.
> >>
> >> Add RISCV_ISA_ZAAMO and RISCV_ISA_ZALRSC. Both default on, and that
> >> selection still passes "a" in -march. Zaamo can be turned off only
> >> with CONFIG_NONPORTABLE; Zalrsc remains required because cmpxchg and
> >> the conditional atomics are LR/SC sequences. An LR/SC-only build
> >> passes _zalrsc instead of "a".
> >>
> >> Suggested-by: Chao-ying Fu <cfu at wavecomp.com>
> >> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev at mobileye.com>
> > 
> > As you can see by the lkp reports, this is not the right way to do this.
> 
> I fixed these lkp reported bugs in v4 by TOOLCHAIN_HAS_ZALRSC that test
> compiler support of _zalrsc in -march

Right, I'll go conjure up a reply to v4 so.
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