[PATCH v7 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain
fangyu.yu at linux.alibaba.com
fangyu.yu at linux.alibaba.com
Tue Nov 3 04:02:33 PST 2026
From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
Replace .domain_alloc_paging with .domain_alloc_paging_flags so callers
can pass allocation flags to select the appropriate page-table type.
When IOMMU_HWPT_ALLOC_NEST_PARENT or IOMMU_HWPT_ALLOC_DIRTY_TRACKING is
set in @flags, allocate a second-stage (iohgatp) domain.
When @flags is 0 the behaviour is identical to the previous
domain_alloc_paging: first-stage (iosatp) domain.
Signed-off-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>
---
drivers/iommu/riscv/iommu.c | 107 ++++++++++++++++++++++++++++--------
1 file changed, 84 insertions(+), 23 deletions(-)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 5546dfcd976c..61dfde11ba13 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1381,25 +1381,74 @@ static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = {
.flush_iotlb_all = riscv_iommu_iotlb_flush_all,
};
-static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
+static int riscv_iommu_init_domain_s1(struct device *dev,
+ struct riscv_iommu_domain *domain,
+ struct pt_iommu_riscv_64_cfg *cfg)
{
- struct pt_iommu_riscv_64_cfg cfg = {};
- struct riscv_iommu_domain *domain;
- struct riscv_iommu_device *iommu;
- int ret;
+ struct riscv_iommu_device *iommu = dev_to_iommu(dev);
- iommu = dev_to_iommu(dev);
+ cfg->common.features |= BIT(PT_FEAT_SIGN_EXTEND);
if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57) {
- cfg.common.hw_max_vasz_lg2 = 57;
+ cfg->common.hw_max_vasz_lg2 = 57;
} else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48) {
- cfg.common.hw_max_vasz_lg2 = 48;
+ cfg->common.hw_max_vasz_lg2 = 48;
} else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39) {
- cfg.common.hw_max_vasz_lg2 = 39;
+ cfg->common.hw_max_vasz_lg2 = 39;
} else {
dev_err(dev, "cannot find supported page table mode\n");
- return ERR_PTR(-ENODEV);
+ return -ENODEV;
}
- cfg.common.hw_max_oasz_lg2 = 56;
+
+ domain->pscid = ida_alloc_range(&riscv_iommu_pscids, 1,
+ RISCV_IOMMU_MAX_PSCID, GFP_KERNEL);
+ if (domain->pscid < 0)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/*
+ * Second-stage (iohgatp) page table for KVM VFIO device pass-through and dirty
+ * tracking. The GPA space is 2 bits wider than the corresponding first-stage VA
+ * space (x4 root page table), so hw_max_vasz_lg2 values are 41/50/59.
+ */
+static int riscv_iommu_init_domain_s2(struct device *dev,
+ struct riscv_iommu_domain *domain,
+ struct pt_iommu_riscv_64_cfg *cfg)
+{
+ struct riscv_iommu_device *iommu = dev_to_iommu(dev);
+
+ cfg->common.features |= BIT(PT_FEAT_RISCV_S2);
+ if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4) {
+ cfg->common.hw_max_vasz_lg2 = 59;
+ } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4) {
+ cfg->common.hw_max_vasz_lg2 = 50;
+ } else if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4) {
+ cfg->common.hw_max_vasz_lg2 = 41;
+ } else {
+ dev_err(dev, "cannot find supported page table mode\n");
+ return -ENODEV;
+ }
+
+ domain->gscid = ida_alloc_range(&riscv_iommu_gscids, 1,
+ RISCV_IOMMU_MAX_GSCID, GFP_KERNEL);
+ if (domain->gscid < 0)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static struct iommu_domain *
+riscv_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags,
+ const struct iommu_user_data *user_data)
+{
+ struct pt_iommu_riscv_64_cfg cfg = {};
+ struct riscv_iommu_domain *domain;
+ struct riscv_iommu_device *iommu;
+ int ret;
+
+ if (user_data)
+ return ERR_PTR(-EOPNOTSUPP);
domain = kzalloc_obj(*domain);
if (!domain)
@@ -1407,12 +1456,13 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
INIT_LIST_HEAD_RCU(&domain->bonds);
spin_lock_init(&domain->lock);
+ iommu = dev_to_iommu(dev);
+ cfg.common.hw_max_oasz_lg2 = 56;
/*
* 6.4 IOMMU capabilities [..] IOMMU implementations must support the
* Svnapot standard extension for NAPOT Translation Contiguity.
*/
- cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) |
- BIT(PT_FEAT_FLUSH_RANGE) |
+ cfg.common.features = BIT(PT_FEAT_FLUSH_RANGE) |
BIT(PT_FEAT_RISCV_SVNAPOT_64K) |
BIT(PT_FEAT_DETAILED_GATHER);
if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT)
@@ -1420,19 +1470,30 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev)
domain->riscvpt.iommu.nid = dev_to_node(iommu->dev);
domain->domain.ops = &riscv_iommu_paging_domain_ops;
- domain->pscid = ida_alloc_range(&riscv_iommu_pscids, 1,
- RISCV_IOMMU_MAX_PSCID, GFP_KERNEL);
- if (domain->pscid < 0) {
- riscv_iommu_free_paging_domain(&domain->domain);
- return ERR_PTR(-ENOMEM);
+ switch (flags) {
+ case 0:
+ ret = riscv_iommu_init_domain_s1(dev, domain, &cfg);
+ break;
+ case IOMMU_HWPT_ALLOC_NEST_PARENT:
+ case IOMMU_HWPT_ALLOC_DIRTY_TRACKING:
+ case IOMMU_HWPT_ALLOC_DIRTY_TRACKING | IOMMU_HWPT_ALLOC_NEST_PARENT:
+ ret = riscv_iommu_init_domain_s2(dev, domain, &cfg);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
}
+ if (ret)
+ goto err_free;
ret = pt_iommu_riscv_64_init(&domain->riscvpt, &cfg, GFP_KERNEL);
- if (ret) {
- riscv_iommu_free_paging_domain(&domain->domain);
- return ERR_PTR(ret);
- }
+ if (ret)
+ goto err_free;
return &domain->domain;
+
+err_free:
+ riscv_iommu_free_paging_domain(&domain->domain);
+ return ERR_PTR(ret);
}
static int riscv_iommu_attach_blocking_domain(struct iommu_domain *iommu_domain,
@@ -1567,7 +1628,7 @@ static const struct iommu_ops riscv_iommu_ops = {
.identity_domain = &riscv_iommu_identity_domain,
.blocked_domain = &riscv_iommu_blocking_domain,
.release_domain = &riscv_iommu_blocking_domain,
- .domain_alloc_paging = riscv_iommu_alloc_paging_domain,
+ .domain_alloc_paging_flags = riscv_iommu_domain_alloc_paging_flags,
.device_group = riscv_iommu_device_group,
.probe_device = riscv_iommu_probe_device,
.release_device = riscv_iommu_release_device,
--
2.50.1
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