[PATCH 7/8] riscv: dts: openhwgroup: add CVA6 APU on Digilent Genesys 2
marouene.boubakri at oss.nxp.com
marouene.boubakri at oss.nxp.com
Mon Nov 2 06:17:26 PST 2026
From: Marouene Boubakri <marouene.boubakri at oss.nxp.com>
The CVA6 APU is the FPGA SoC built around the OpenHW Group CVA6 core in
the CVA6 repository (corev_apu/fpga, release v5.3.0). It targets the
Digilent Genesys 2 board and provides a CLINT, a PLIC, a 16550 UART, a
Xilinx SPI controller connected to the SD card slot and a Xilinx GPIO
block driving the LEDs.
Describe the SoC in cva6-genesys2.dtsi, shared by the two configurations
of the core that the FPGA platform builds, and add a board device tree
for each of them:
- cv64a6: rv64imafdc with the B, Zcb, Zicond and Zkn extensions,
Sv39, 1 GiB of DDR3
- cv32a6: rv32ima, Sv32, 128 MiB of DDR3
The ISA extensions follow the core configurations of CVA6 v5.3.0
(core/include/cv64a6_imafdc_sv39_config_pkg.sv and
cv32a6_ima_sv32_fpga_config_pkg.sv).
The platform also has a lowRISC Ethernet controller and a PULP APB
timer. They are left out until bindings exist for them.
Signed-off-by: Marouene Boubakri <marouene.boubakri at oss.nxp.com>
---
MAINTAINERS | 7 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/openhwgroup/Makefile | 2 +
.../boot/dts/openhwgroup/cv32a6-genesys2.dts | 29 ++++
.../boot/dts/openhwgroup/cv64a6-genesys2.dts | 31 +++++
.../boot/dts/openhwgroup/cva6-genesys2.dtsi | 131 ++++++++++++++++++
6 files changed, 201 insertions(+)
create mode 100644 arch/riscv/boot/dts/openhwgroup/Makefile
create mode 100644 arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
create mode 100644 arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
create mode 100644 arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 782389bd5c..17865074a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23566,6 +23566,13 @@ T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: arch/riscv/boot/dts/canaan/
F: arch/riscv/boot/dts/sifive/
+RISC-V OPENHW GROUP SoC SUPPORT
+M: Marouene Boubakri <marouene.boubakri at oss.nxp.com>
+L: linux-riscv at lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/riscv/openhwgroup.yaml
+F: arch/riscv/boot/dts/openhwgroup/
+
RISC-V PMU DRIVERS
M: Atish Patra <atish.patra at linux.dev>
R: Anup Patel <anup at brainfault.org>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb1..305a93ad6f 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -5,6 +5,7 @@ subdir-y += anlogic
subdir-y += canaan
subdir-y += eswin
subdir-y += microchip
+subdir-y += openhwgroup
subdir-y += renesas
subdir-y += sifive
subdir-y += sophgo
diff --git a/arch/riscv/boot/dts/openhwgroup/Makefile b/arch/riscv/boot/dts/openhwgroup/Makefile
new file mode 100644
index 0000000000..a75a5863b7
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_OPENHWGROUP) += cv32a6-genesys2.dtb cv64a6-genesys2.dtb
diff --git a/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
new file mode 100644
index 0000000000..83d0286171
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU, 32-bit core (cv32a6), on the Digilent Genesys 2.
+ */
+
+/dts-v1/;
+
+#include "cva6-genesys2.dtsi"
+
+/ {
+ model = "OpenHW Group CVA6 cv32a6 on Digilent Genesys 2";
+ compatible = "openhwgroup,cv32a6-genesys2", "openhwgroup,cva6-apu";
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 128 MiB of DDR3, as configured for this core by the FPGA build */
+ reg = <0x0 0x80000000 0x0 0x8000000>;
+ };
+};
+
+&cpu0 {
+ compatible = "openhwgroup,cv32a6", "riscv";
+ riscv,isa-base = "rv32i";
+ riscv,isa-extensions = "i", "m", "a", "zicntr", "zicsr", "zifencei",
+ "zihpm";
+ mmu-type = "riscv,sv32";
+};
diff --git a/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
new file mode 100644
index 0000000000..8fe653b35c
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU, 64-bit core (cv64a6), on the Digilent Genesys 2.
+ */
+
+/dts-v1/;
+
+#include "cva6-genesys2.dtsi"
+
+/ {
+ model = "OpenHW Group CVA6 cv64a6 on Digilent Genesys 2";
+ compatible = "openhwgroup,cv64a6-genesys2", "openhwgroup,cva6-apu";
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 1 GiB of DDR3, as configured for this core by the FPGA build */
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+};
+
+&cpu0 {
+ compatible = "openhwgroup,cv64a6", "riscv";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "zba",
+ "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs",
+ "zca", "zcb", "zcd", "zicntr", "zicond", "zicsr",
+ "zifencei", "zihpm", "zknd", "zkne", "zknh";
+ mmu-type = "riscv,sv39";
+};
diff --git a/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
new file mode 100644
index 0000000000..95978274a7
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU on the Digilent Genesys 2 FPGA board.
+ *
+ * The SoC description is shared between the 32-bit (cv32a6) and the
+ * 64-bit (cv64a6) configurations of the CVA6 core. The core specific
+ * properties and the memory size are set in the board .dts files.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* The CLINT mtime counter runs at half the core clock */
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <50000000>;
+ tlb-split;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+
+ /* Peripheral clock, the same as the core clock */
+ clk50: clock-50mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clk50";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ gpios = <&gpio0 1 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ clint: clint at 2000000 {
+ compatible = "openhwgroup,cva6-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+
+ plic: interrupt-controller at c000000 {
+ compatible = "openhwgroup,cva6-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ riscv,ndev = <30>;
+ };
+
+ uart0: serial at 10000000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clock-frequency = <50000000>;
+ interrupt-parent = <&plic>;
+ interrupts = <1>;
+ /* Registers are 32-bit wide and 32-bit aligned */
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ spi0: spi at 20000000 {
+ compatible = "xlnx,xps-spi-2.00.a";
+ reg = <0x0 0x20000000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <2>;
+ xlnx,num-ss-bits = <1>;
+ xlnx,num-transfer-bits = <8>;
+
+ mmc at 0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <12500000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+ };
+
+ gpio0: gpio at 40000000 {
+ compatible = "xlnx,xps-gpio-1.00.a";
+ reg = <0x0 0x40000000 0x0 0x10000>;
+ clocks = <&clk50>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ xlnx,all-inputs = <0>;
+ xlnx,all-inputs-2 = <0>;
+ xlnx,dout-default = <0>;
+ xlnx,dout-default-2 = <0>;
+ xlnx,gpio-width = <8>;
+ xlnx,gpio2-width = <8>;
+ xlnx,interrupt-present = <0>;
+ xlnx,is-dual = <1>;
+ xlnx,tri-default = <0xffffffff>;
+ xlnx,tri-default-2 = <0xffffffff>;
+ };
+ };
+};
--
2.43.0
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