From: Marouene Boubakri <marouene.boubakri at oss.nxp.com>
This series adds support for the OpenHW Group CVA6 APU, the FPGA SoC
built around the CVA6 core (https://github.com/openhwgroup/cva6,
corev_apu/fpga, release v5.3.0), running on the Digilent Genesys 2.
Both configurations of the core built for this board are covered: the
64-bit cv64a6 (rv64imafdc plus B, Zcb, Zicond and Zkn, Sv39, 1 GiB) and
the 32-bit cv32a6 (rv32ima, Sv32, 128 MiB). The SoC description is
shared in a dtsi and the two board .dts files only carry the core
specific properties and the memory size.
The peripherals use existing bindings: 8250 UART, Xilinx SPI with an
mmc-spi-slot, Xilinx GPIO with gpio-leds, SiFive compatible CLINT and
PLIC. Patches 1 to 5 add the vendor prefix and the compatible strings
these bindings need, patch 6 the ARCH_OPENHWGROUP Kconfig option,
patch 7 the device trees and the MAINTAINERS entry, patch 8 enables the
platform in the defconfig.
The lowRISC Ethernet controller and the PULP timer of the platform have
no upstream bindings yet and are left out of the device trees.
The device trees have been validated with dtbs_check. The cv64a6
configuration has been booted on the Genesys 2 from U-Boot 2026.10 with
the board support submitted to U-Boot, using the same device tree
content as this series. The cv32a6 configuration is build tested.
Marouene Boubakri (8):
dt-bindings: vendor-prefixes: add OpenHW Group
dt-bindings: riscv: cpus: add OpenHW Group CVA6 compatibles
dt-bindings: timer: sifive,clint: add OpenHW Group CVA6 APU
dt-bindings: interrupt-controller: sifive,plic: add OpenHW Group CVA6
APU
dt-bindings: riscv: add OpenHW Group CVA6 APU boards
riscv: add ARCH_OPENHWGROUP Kconfig option
riscv: dts: openhwgroup: add CVA6 APU on Digilent Genesys 2
riscv: defconfig: enable OpenHW Group CVA6 APU support
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/cpus.yaml | 2 +
.../bindings/riscv/openhwgroup.yaml | 30 +++++
.../bindings/timer/sifive,clint.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 7 +
arch/riscv/Kconfig.socs | 6 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/openhwgroup/Makefile | 2 +
.../boot/dts/openhwgroup/cv32a6-genesys2.dts | 29 +++++
.../boot/dts/openhwgroup/cv64a6-genesys2.dts | 31 +++++
.../boot/dts/openhwgroup/cva6-genesys2.dtsi | 123 ++++++++++++++++++
arch/riscv/configs/defconfig | 3 +
13 files changed, 238 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/openhwgroup.yaml
create mode 100644 arch/riscv/boot/dts/openhwgroup/Makefile
create mode 100644 arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
create mode 100644 arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
create mode 100644 arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
--
2.43.0