[PATCH] irqchip/riscv-imsic: Use GENMASK for base address masks

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Thomas Gleixner <tglx at kernel.org>:

On Sat, 18 Jul 2026 12:34:36 +0800 you wrote:
> The IMSIC DT binding allows riscv,guest-index-bits up to 7 and
> riscv,hart-index-bits up to 15. On RV32, guest-index-bits=7 and
> hart-index-bits=13, together with the 12-bit IMSIC page offset, is a
> binding-valid layout that consumes a 32-bit low-address mask.
> 
> The parser accepts this equality case because it rejects only values
> larger than the remaining bit budget. The base address canonicalization
> then builds the low-address mask with BIT(sum) - 1. When sum is 32 on
> RV32, that expression shifts an unsigned long by its full width.
> 
> [...]

Here is the summary with links:
  - irqchip/riscv-imsic: Use GENMASK for base address masks
    https://git.kernel.org/riscv/c/bd7d57a03c4b

You are awesome, thank you!
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