[PATCH v13 3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux

[Rob Herring (Arm)]

On Wed, 18 Mar 2026 11:04:34 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> On PolarFire SoC there are more GPIO interrupts than there are interrupt
> lines available on the PLIC, and a runtime configurable mux is used to
> decide which interrupts are assigned direct connections to the PLIC &
> which are relegated to sharing a line.
> 
> Reviewed-by: Herve Codina <herve.codina at bootlin.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  .../soc/microchip/microchip,mpfs-irqmux.yaml  | 103 ++++++++++++++++++
>  .../microchip,mpfs-mss-top-sysreg.yaml        |   4 +
>  2 files changed, 107 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh at kernel.org>