[PATCH v2 08/10] gpu: nova-core: convert falcon registers to kernel register macro
Joel Fernandes
joelagnelf at nvidia.com
Fri Mar 20 10:38:25 PDT 2026
Hi Alex,
On 3/20/2026 8:19 AM, Alexandre Courbot wrote:
> /// Reset the controller, select the falcon core, and wait for memory scrubbing to complete.
> @@ -616,9 +462,10 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result {
> self.hal.select_core(self, bar)?;
> self.hal.reset_wait_mem_scrubbing(bar)?;
>
> - regs::NV_PFALCON_FALCON_RM::default()
> - .set_value(bar.read(regs::NV_PMC_BOOT_0).into())
> - .write(bar, &E::ID);
> + bar.write(
> + WithBase::of::<E>(),
> + regs::NV_PFALCON_FALCON_RM::from(bar.read(regs::NV_PMC_BOOT_0).into_raw()),
> + );
>
Overall, I think the series is good improvement but I still feel this part is a
step back in readability, and we should come up with something better. I don't
think there's any chance anyone can memorize this syntax.
What about using a macro to hide the boilerplate?
> Ok(())
> }
> @@ -636,25 +483,27 @@ fn pio_wr_imem_slice(&self, bar: &Bar0, load_offsets: FalconPioImemLoadTarget<'_
> return Err(EINVAL);
> }
>
> - regs::NV_PFALCON_FALCON_IMEMC::default()
> - .set_secure(load_offsets.secure)
> - .set_aincw(true)
> - .set_offs(load_offsets.dst_start)
> - .write(bar, &E::ID, Self::PIO_PORT);
> + bar.write(
> + WithBase::of::<E>().at(Self::PIO_PORT),
> + regs::NV_PFALCON_FALCON_IMEMC::zeroed()
> + .with_secure(load_offsets.secure)
> + .with_aincw(true)
> + .with_offs(load_offsets.dst_start),
> + );
And bare minimum, probably the inner:
> + regs::NV_PFALCON_FALCON_IMEMC::zeroed()
> + .with_secure(load_offsets.secure)
> + .with_aincw(true)
> + .with_offs(load_offsets.dst_start),
Should be assigned to a separate variable for readability. I think otherwise it
is quite unbeatable.
thanks,
--
Joel Fernandes
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