[PATCH v13 1/5] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation

[Linus Walleij]

On Wed, Mar 18, 2026 at 12:04 PM Conor Dooley <conor at kernel.org> wrote:

> From: Conor Dooley <conor.dooley at microchip.com>
>
> The microchip,mpfs-gpio binding suffered greatly due to being written
> with a narrow minded view of the controller, and the interrupt bits
> ended up incorrect. It was mistakenly assumed that the interrupt
> configuration was set by platform firmware, based on the FPGA
> configuration, and that the GPIO DT nodes were the only way to really
> communicate interrupt configuration to software.
>
> Instead, the mux should be a device in its own right, and the GPIO
> controllers should be connected to it, rather than to the PLIC.
> Now that a binding exists for that mux, try to fix the misconceptions
> in the GPIO controller binding.
>
> Firstly, it's not possible for this controller to have fewer than 14
> GPIOs, and thus 14 interrupts also. There are three controllers, with
> 14, 24 & 32 GPIOs each. The fabric core, CoreGPIO, can of course have
> a customisable number of GPIOs.
>
> The example is wacky too - it follows from the incorrect understanding
> that the GPIO controllers are connected to the PLIC directly. They are
> not however, with a mux sitting in between. Update the example to use
> the mux as a parent, and the interrupt numbers at the mux for GPIO2 as
> the example - rather than the strange looking, repeated <53>.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Makes sense to me!
Reviewed-by: Linus Walleij <linusw at kernel.org>

Yours,
Linus Walleij