[PATCH 1/3] dt-bindings: usb: dwc3: spacemit: add support for K3 SoC

[Yixun Lan]

Hi Conor,

On 14:36 Thu 19 Mar     , Conor Dooley wrote:
> On Thu, Mar 19, 2026 at 10:41:24AM +0800, Yixun Lan wrote:
> > Hi Conor,
> > 
> > On 17:21 Wed 18 Mar     , Conor Dooley wrote:
> > > On Wed, Mar 18, 2026 at 05:44:35AM +0800, Yixun Lan wrote:
> > > > Hi Conor,
> > > > 
> > > > On 12:55 Tue 17 Mar     , Conor Dooley wrote:
> > > > > On Tue, Mar 17, 2026 at 11:53:02AM +0000, Yixun Lan wrote:
> > > > > > Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
> > > > > > The USB2.0 host controller in K3 SoC actually use DWC3 IP but only has
> > > > > > USB2.0 functionality, and requires only one USB2.0 PHY connected.
> > > > > > 
> > > > > > Explicitly reduce number of phy property to minimal one.
> > > > > 
> > > > > Is this valid for the existing compatible, will it work with only one
> > > > > clock?
> > > > > 
> > > > I didn't change clock binding, do you mean phy?
> > > > 
> > > > Both k1 and k3 work with one clock (no change here)
> > > > 
> > > > for phy, the existing k1 requires two. for k3, one controller requires
> > > > one phy due to only has USB2.0 support, other controllers requires two
> > > > phys - USB2, USB3 PHY
> > > 
> > > Yep, phy is what I meant. Sorry bout that. Since you're relaxing the
> > > constraints for the k1, can you please add a conditional section to the
> > > binding to enforce 2 phys min for k1?
> > > 
> > 
> > To be explicit, the change should be applied to both K1 and K3, even in K1
> > use case, it's perfectly fine for designer to choose enabling USB2.0
> > only, and leave the comb phy to pcie contoller, so only one phy required
> 
> In that case, can you be more clear in the commit message about why this
> is also being done for the k1 please?

sure, I will do it in v2

-- 
Yixun Lan (dlan)