[PATCH net-next v4 1/3] dt-bindings: ethernet: eswin: add clock sampling control

[李志]

Hi Krzysztof,

Could you please take a look at Conor’s feedback on the compatible naming?

Conor has reviewed the patch and provided his Acked-by, but also noted
that there might be concerns regarding the compatible string.

Please let me know if the current naming is acceptable, or if any changes
are required.

Thanks,
Zhi Li


> -----原始邮件-----
> 发件人: "Conor Dooley" <conor at kernel.org>
> 发送时间:2026-03-14 01:39:58 (星期六)
> 收件人: lizhi2 at eswincomputing.com
> 抄送: devicetree at vger.kernel.org, andrew+netdev at lunn.ch, davem at davemloft.net, edumazet at google.com, kuba at kernel.org, robh at kernel.org, krzk+dt at kernel.org, conor+dt at kernel.org, netdev at vger.kernel.org, pabeni at redhat.com, mcoquelin.stm32 at gmail.com, alexandre.torgue at foss.st.com, rmk+kernel at armlinux.org.uk, wens at kernel.org, pjw at kernel.org, palmer at dabbelt.com, aou at eecs.berkeley.edu, alex at ghiti.fr, linux-riscv at lists.infradead.org, linux-stm32 at st-md-mailman.stormreply.com, linux-arm-kernel at lists.infradead.org, linux-kernel at vger.kernel.org, ningyu at eswincomputing.com, linmin at eswincomputing.com, pinkesh.vaghela at einfochips.com, pritesh.patel at einfochips.com, weishangjuan at eswincomputing.com
> 主题: Re: [PATCH net-next v4 1/3] dt-bindings: ethernet: eswin: add clock sampling control
> 
> On Fri, Mar 13, 2026 at 03:53:51PM +0800, lizhi2 at eswincomputing.com wrote:
> > From: Zhi Li <lizhi2 at eswincomputing.com>
> > 
> > Due to chip backend reasons, there is already an approximately 4-5 ns
> > skew between the RX clock and data of the eth1 MAC controller inside
> > the silicon.
> > 
> > For 1000M, the RX clock must be inverted since it is not possible to
> > meet the RGMII timing requirements using only rx-internal-delay-ps on
> > the MAC together with the standard 2 ns delay on the PHY. Therefore,
> > even on a properly designed board, eth1 still requires RX clock
> > inversion.
> > 
> > This behaviour effectively breaks the RGMII timing assumptions at the
> > SoC level.
> > 
> > For the TX path of eth1, there is also a skew between the TX clock
> > and data on the MAC controller inside the silicon. This skew happens
> > to be approximately 2 ns. Therefore, it can be considered that the
> > 2 ns delay of TX is provided by the MAC, so the TX is compliant with
> > the RGMII standard.
> > 
> > For 10/100 operation, the approximately 4-5 ns skew in the chip does
> > not break the standard. The RGMII timing table (Section 3.3) specifies
> > that for 10/100 operation the maximum value is unspecified:
> > https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/20655/1/RGMIIv2_0_final_hp.pdf
> > 
> > Due to the eth1 silicon behavior described above, a new compatible
> > string "eswin,eic7700-qos-eth-clk-inversion" is added to the device
> > tree. This allows the driver to handle the differences between eth1
> > and eth0 through dedicated logic.
> > 
> > The rx-internal-delay-ps and tx-internal-delay-ps properties now use
> > minimum and maximum constraints to reflect the actual hardware delay
> > range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
> > validation compared to the previous enum-based definition and avoids
> > regressions for existing DTBs while keeping the same hardware limits.
> > 
> > Treat the RX/TX internal delay properties as optional, board-specific
> > tuning knobs and remove them from the example to avoid encouraging
> > their use.
> > 
> > In addition, the binding now includes additional background information
> > about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
> > control registers are included so the driver can explicitly clear any
> > residual configuration left by the bootloader.
> > 
> > Background reference for the High-Speed Subsystem and HSP CSR block is
> > available in Chapter 10 ("High-Speed Interface") of the EIC7700X SoC
> > Technical Reference Manual, Part 4
> > (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
> > https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
> > 
> > There are currently no in-tree users of the EIC7700 Ethernet driver, so
> > these changes are safe.
> > 
> > Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
> > Signed-off-by: Zhi Li <lizhi2 at eswincomputing.com>
> 
> Krzysztof might not yet be happy with the compatible naming, but from my
> pov:
> Acked-by: Conor Dooley <conor.dooley at microchip.com>