[PATCH v3 1/2] riscv: Introduce support for hardware break/watchpoints

[Ilya Mamay]

Hi,

Thank you for this patch - it;s a valuable addition to the RISC-V HBP support.
I have one question regarding the locking:

On Mon, Feb 23, 2026 at 10:19:17AM +0530, Himanshu Chauhan wrote:
> +int arch_install_hw_breakpoint(struct perf_event *event)
> +{
> +	struct arch_hw_breakpoint *bp = counter_arch_bp(event);
> +	union sbi_dbtr_shmem_entry *shmem = this_cpu_ptr(sbi_dbtr_shmem);
> +	struct sbi_dbtr_data_msg *xmit;
> +	struct sbi_dbtr_id_msg *recv;
> +	struct perf_event **slot;
> +	unsigned long idx;
> +	struct sbiret ret;
> +	int err = 0;
> +
> +	raw_spin_lock_irqsave(this_cpu_ptr(&ecall_lock),
> +			      *this_cpu_ptr(&ecall_lock_flags));

Could you clarify the purpose of the ecall_lock in arch_install_hw_breakpoint and 
arch_update_hw_breakpoint? Why is it used only in two functions mentioned above,
but not in other PMU callbacks like arch_uninstall_hw_breakpoint?

Regards
Ilya

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