[PATCH v2] iommu/riscv: Add IOTINVAL after updating DDT/PDT entries

[Jörg Rödel]

On Thu, Jan 22, 2026 at 10:32:24PM +0800, fangyu.yu at linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> 
> Add riscv_iommu_iodir_iotinval() to perform required TLB and context cache
> invalidations after updating DDT or PDT entries, as mandated by the RISC-V
> IOMMU specification (Section 6.3.1 and 6.3.2).
> 
> Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support")
> Signed-off-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> Reviewed-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> 
> ---
>     Changes in v2:
>     - Reworked the patch formatting (per Drew).
>     - Fixed the call site of riscv_iommu_iodir_iotinval() (per Drew).
>     - Moved riscv_iommu_cmd_inval_vma() out of the conditional blocks to avoid
>       duplication (per Guoren).
>     - Dropped the #if 0-guarded code (per Guoren).
>     - Updated the Fixes: tag (per Drew).
>     - Link to v1:
>       https://lore.kernel.org/linux-riscv/20260108134855.91341-1-fangyu.yu@linux.alibaba.com/
> ---
>  drivers/iommu/riscv/iommu.c | 70 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)

Applied, thanks.