[PATCH 3/4] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller

[Krzysztof Kozlowski]

On 16/03/2026 08:06, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia at ultrarisc.com>
> 
> Add UltraRISC DP1000 SoC PCIe controller devicetree bindings.
> 
> Signed-off-by: Jia Wang <wangjia at ultrarisc.com>
> ---
>  .../bindings/pci/ultrarisc,dp1000-pcie.yaml        | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> new file mode 100644
> index 000000000000..b50ff98dd878
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 PCIe Host Controller
> +
> +description: |
> +  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
> +  This binding describes the UltraRISC specific extensions to the base DesignWare
> +  PCIe binding.
> +
> +maintainers:
> +  - Xincheng Zhang <zhangxincheng at ultrarisc.com>
> +  - Jia Wang <wangjia at ultrarisc.com>
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    const: ultrarisc,dp1000-pcie
> +
> +  reg:
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.

Never tested. Test your patches before sending to avoid common mistakes.
Several issues here are just duplicating known issue.

Read also sashiko review of your code.

https://sashiko.dev/#/patchset/20260316-ultrarisc-pcie-v1-0-ef2946ede698%40ultrarisc.com

Best regards,
Krzysztof