[PATCH v12 4/4] riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC

[Linus Walleij]

On Wed, Mar 11, 2026 at 4:18 PM Conor Dooley <conor at kernel.org> wrote:

> From: Conor Dooley <conor.dooley at microchip.com>
>
> There are 3 GPIO controllers on this SoC, of which:
> - GPIO controller 0 has 14 GPIOs
> - GPIO controller 1 has 24 GPIOs
> - GPIO controller 2 has 32 GPIOs
>
> All GPIOs are capable of generating interrupts, for a total of 70.
> There are only 41 IRQs available however, so a configurable mux is used
> to ensure all GPIOs can be used for interrupt generation.
> 38 of the 41 interrupts are in what the documentation calls "direct
> mode", as they provide an exclusive connection from a GPIO to the PLIC.
> The 3 remaining interrupts are used to mux the interrupts which do not
> have a exclusive connection, one for each GPIO controller.
>
> The mux was overlooked when the bindings and driver were originally
> written for the GPIO controllers on Polarfire SoC, and the interrupts
> property in the GPIO nodes used to try and convey what the mapping was.
> Instead, the mux should be a device in its own right, and the GPIO
> controllers should be connected to it, rather than to the PLIC.
> Now that a binding exists for that mux, fix the inaccurate description
> of the interrupt controller hierarchy.
>
> GPIO controllers 0 and 1 do not have all 32 possible GPIO lines, so
> ngpios needs to be set to match the number of lines/interrupts.
>
> The m100pfsevp has conflicting interrupt mappings for controllers 0 and
> 2, as they cannot both be using an interrupt in "direct mode" at the
> same time, so the default replaces this impossible configuration.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Reviewed-by: Linus Walleij <linusw at kernel.org>

Yours,
Linus Walleij