[PATCH v12 1/4] gpio: mpfs: Add interrupt support

[Bartosz Golaszewski]

On Wed, 11 Mar 2026 16:17:38 +0100, Conor Dooley <conor at kernel.org> said:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> Add support for interrupts to the PolarFire SoC GPIO driver. Each GPIO
> has an independent interrupt that is wired to an interrupt mux that sits
> between the controllers and the PLIC. The SoC has more GPIO lines than
> connections from the mux to the PLIC, so some GPIOs must share PLIC
> interrupts. The configuration is not static and is set at runtime,
> conventionally by the platform's firmware. CoreGPIO, the version
> intended for use in the FPGA fabric has two interrupt output ports, one
> is IO_NUM bits wide, as is used in the hardened cores, and the other is
> a single bit with all lines ORed together.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---

Acked-by: Bartosz Golaszewski <bartosz.golaszewski at oss.qualcomm.com>