[RFC PATCH 1/6] riscv: Add a custom, simplified version of Svpbmt "XPbmtUC"

[Bo Gan]

Hi Conor,

Thanks so much for the prompt review. See inline.

On 3/13/26 06:24, Conor Dooley wrote:
> Hey,
> 
> Gonna offer some feedback on the detail of what's been done in this
> series, without providing any commentary on whether this is the correct
> approach to take.
> 
> On Fri, Mar 13, 2026 at 01:44:02AM -0700, Bo Gan wrote:
>> On platforms that doesn't support Svpbmt or XTheadMae, SoC vendors
>> sometimes map the system memory twice in physical address space, one
>> as cached, and the other as uncached. Through the uncached window,
>> device drivers will be able to map DMA buffer for noncoherent devices.
>> Such setup is usually found in SoC with pre-Svpbmt Sifive cores.
>> Make use of such feature by modeling it as "XPbmtUC", a customized
>> version of Svpbmt, where a single bit in PTE is used for UC control.
>> There's no IO bit with such scheme, as it's assumed that the PMA
>> (usually hard-wired on these SoCs) will properly convey the strongly-
>> ordered, non-idempotent attribute of the MMIO region.
>>
>> The enablement of such position of "XPbmtUC" is controlled by the
>> device-tree property "riscv,xpbmt-uncache-bit".
> 
> Firstly, the naming generally I take some exception to. If this is some
> fake vendor extension for linux purposes, it needs to have "xlinux" in
> it, like our xlinuxenvcfg does. It should also be consistent, don't use
> "xpmbtuc" and "xpbmt-uncache-bit", pick one and stick to it.
> 
Makes sense. I can certainly change that to be conformant.

> Athough, I think I disagree fundamentally with this property, as it seems
> to me like "software configuration" that shouldn't be permitted in
> devicetree. Maybe I am misunderstanding, but the numbers you chose are
> convenient, not set in stone by the specific hardware, right?

For JH7110, the bit 32 (PPN bit 34) matches exactly with the HW. Meaning
toggling this bit would re-map the page to the uncached window, which
matches perfectly with the synthetic UC bit in the scheme.

For EIC770X, the bit 38 (PPN bit 40) is hand picked to be able to map all
physical memory space (40 bit), while making it very easy for the thin-
hypervisor, which can utilize Sv39x4 (41 bit) page scheme in G-stage.

I also considered the sbi call approach, where the kernel can query for
the support and position of the uncache bit. The thing is that JH7110
can just hard-code the bit without any changes to firmware, and I want
to have a consistent way for both SoC, thus the device-tree approach, to
let the EIC770X firmware/bootloader adding the property to dt at runtime.
Any better ideas?

> 
> I'd be much more comfortable with adding xlinuxwhatever to
> riscv,isa-extensions, to signal that a soc supports this stuff than with
> a property for the bit itself. I suppose that bit information could then
> come from a LUT in the vendor extensions, that a validate callback could
> check (via root compatible) before enabling. There's not a super neat
> way to do that at the moment though I don't think, code currently
> expects that vendor extensions are in a different "namespace" to
> standard ones, and this would blur the lines because it's not from a
> specific vendor, nor is it a standard extension.
> I guess, it could be done by keeping it as a standard number, but then
> it's a bit trickier to neatly access the LUT while keeping it split
> apart.
> I know this means having to modify the kernel if there's a new device,
> but I'm inclined to say "deal with it" because they could've done
> something standard and opted not to.
> 
> Could also argue that this should be shoved into a sifive specific
> thing, but I don't expect that they're the only ones with devices like
> this that could benefit.
> 

I've thought about riscv,isa-extensions. The issue with that is that it's
a per-CPU thing, but I'm adding a global extension, and I don't want to
pollute the isa-extension string. Thus, I followed Samuel's approach --
He uses "riscv,physical-memory-regions" in the root node.

>>
>> Example:
>>
>> Starfive JH7110 (Sifive U74):
>>             [0x0,   0x40000000) Low MMIO
>>      [0x40000000, 0x2_40000000) Cached Mem
>>    [0x4_40000000, 0x6_40000000) Uncached Mem UC+
>>    [0x9_00000000, 0x9_d0000000) High MMIO
>>
>> Device-tree:
>>    riscv,xpbmt-uncache-bit = <32>;
>>
>> Use PTE bit 32 (PPN bit 34) as UC (uncache) control to perfectly
>> match the memory map of the SoC.
>>
>> ESWIN EIC770X (Sifive U84/P550):
>>             [0x0,    0x20000000) Core Internal
>>      [0x20000000,    0x40000000) Core Internal (Die 1)
>>      [0x40000000,    0x60000000) Low MMIO
>>      [0x60000000,    0x80000000) Low MMIO (Die 1)
>>      [0x80000000, 0x10_80000000) Cached Mem
>>   [0x20_00000000, 0x30_00000000) Cached Mem (Die 1)
>>   [0x80_00000000, 0xa0_00000000) High MMIO
>>   [0xa0_00000000, 0xc0_00000000) High MMIO (Die 1)
>>   [0xc0_00000000, 0xd0_00000000) Uncached Mem
>>   [0xe0_00000000, 0xf0_00000000) Uncached Mem (Die 1)
>>
>> EIC770X is not directly compatible to this model, as the uncached
>> regions are offsetted, and the offset is different among the Dies
>> in the dual-die version (EIC7702). so we expect the firmware to
>> provide a thin layer of hypervisor to transparently re-map:
>>
>>      [0x80000000,  0x10_80000000) Cached Mem
>>   [0x20_00000000,  0x30_00000000) Cached Mem (Die 1)
>>   [0xc0_00000000,  0xd0_00000000) Uncached Mem <----------.
>>   [0xe0_00000000,  0xf0_00000000) Uncached Mem (Die 1) <--+--.
>> [0x100_80000000, 0x110_80000000) Mem UC+ ----------------'  |
>> [0x120_00000000, 0x130_00000000) Mem UC+ (Die 1) -----------'
>>
>> With that, the firmware/bootloader can set the following at boot:
>>    riscv,xpbmt-uncache-bit = <38>;
>>
>> Signed-off-by: Bo Gan <ganboing at gmail.com>
>> ---
>>   arch/riscv/Kconfig                  | 12 ++++++++++++
>>   arch/riscv/include/asm/hwcap.h      |  1 +
>>   arch/riscv/include/asm/pgtable-64.h |  8 ++++++++
>>   arch/riscv/kernel/cpufeature.c      |  8 ++++++++
>>   arch/riscv/mm/pgtable.c             |  7 +++++++
>>   5 files changed, 36 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 6b39f37f769a2..f2b4da6a3deb1 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -893,6 +893,18 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
>>   	  versions of clang and GCC to be passed to GAS, which has the same result
>>   	  as passing zicsr and zifencei to -march.
>>   
>> +config RISCV_ISA_XPBMTUC
>> +	bool "Support XPbmtUC (customized pbmt uncache bit)"
>> +	depends on 64BIT && MMU
>> +	depends on RISCV_ALTERNATIVE
>> +	default n
>> +	select DMA_DIRECT_REMAP
>> +	help
>> +	  Add support for "riscv,xpbmt-uncache-bit" device-tree property.
>> +	  The bit denotes the bit in PTE that marks the page as uncached.
>> +
>> +	  If you don't know what to do here, say N.
>> +
>>   config FPU
>>   	bool "FPU support"
>>   	default y
>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> index 4369a23385413..6baa6566cf4cc 100644
>> --- a/arch/riscv/include/asm/hwcap.h
>> +++ b/arch/riscv/include/asm/hwcap.h
>> @@ -111,6 +111,7 @@
>>   #define RISCV_ISA_EXT_ZILSD		102
>>   #define RISCV_ISA_EXT_ZCLSD		103
>>   
>> +#define RISCV_ISA_EXT_XPBMTUC		126
>>   #define RISCV_ISA_EXT_XLINUXENVCFG	127
>>   
>>   #define RISCV_ISA_EXT_MAX		128
>> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
>> index 6e789fa58514c..1a6d04884111d 100644
>> --- a/arch/riscv/include/asm/pgtable-64.h
>> +++ b/arch/riscv/include/asm/pgtable-64.h
>> @@ -140,6 +140,14 @@ enum napot_cont_order {
>>   #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
>>   #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>>   
>> +#ifdef CONFIG_RISCV_ISA_XPBMTUC
>> +extern int riscv_xpbmtuc_bit;
>> +extern u64 riscv_xpbmtuc_mask;
>> +#endif
>> +
>> +#define XPBMTUC_HAS_PAGE_NOCACHE CONFIG_RISCV_ISA_XPBMTUC
>> +#define XPBMTUC_HAS_PAGE_MTMASK  CONFIG_RISCV_ISA_XPBMTUC
>> +
>>   static inline u64 riscv_page_mtmask(void)
>>   {
>>   	u64 val;
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index fa591aff9d335..faec169004b4a 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -1118,6 +1118,14 @@ void __init riscv_fill_hwcap(void)
>>   		riscv_v_setup_vsize();
>>   	}
>>   
>> +#ifdef CONFIG_RISCV_ISA_XPBMTUC
> 
> Code like this needs to be unconditionally compiled.
> 
>> +	if (!of_property_read_u32(of_root, "riscv,xpbmt-uncache-bit",
>> +				  &riscv_xpbmtuc_bit)) {
>> +		riscv_xpbmtuc_mask = 1UL << riscv_xpbmtuc_bit;
>> +		set_bit(RISCV_ISA_EXT_XPBMTUC, riscv_isa);
>> +		pr_info("Using XPbmtUC bit=%d\n", riscv_xpbmtuc_bit);
>> +	}
>> +#endif
>>   	memset(print_str, 0, sizeof(print_str));
>>   	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
>>   		if (riscv_isa[0] & BIT_MASK(i))
>> diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
>> index 807c0a0de1827..4ca442bc8595d 100644
>> --- a/arch/riscv/mm/pgtable.c
>> +++ b/arch/riscv/mm/pgtable.c
>> @@ -5,6 +5,13 @@
>>   #include <linux/kernel.h>
>>   #include <linux/pgtable.h>
>>   
>> +#ifdef CONFIG_RISCV_ISA_XPBMTUC
>> +int riscv_xpbmtuc_bit;
>> +
>> +u64 riscv_xpbmtuc_mask;
>> +EXPORT_SYMBOL(riscv_xpbmtuc_mask);
>> +#endif
>> +
>>   int ptep_set_access_flags(struct vm_area_struct *vma,
>>   			  unsigned long address, pte_t *ptep,
>>   			  pte_t entry, int dirty)
>> -- 
>> 2.34.1
>>

Bo