[RFC PATCH 5/6] riscv: dts: starfive: jh7110: activate XPbmtUC

[Bo Gan]

Set riscv,xpbmt-uncache-bit to 32 to match SoC memory map:

           [0x0,   0x40000000) Low MMIO
    [0x40000000, 0x2_40000000) Cached Mem
  [0x4_40000000, 0x6_40000000) Uncached Mem UC+
  [0x9_00000000, 0x9_d0000000) High MMIO

Signed-off-by: Bo Gan <ganboing at gmail.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 6e56e9d20bb06..6dfeb31538fba 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -14,6 +14,7 @@ / {
 	compatible = "starfive,jh7110";
 	#address-cells = <2>;
 	#size-cells = <2>;
+	riscv,xpbmt-uncache-bit = <32>;
 
 	cpus: cpus {
 		#address-cells = <1>;
-- 
2.34.1