[PATCH 1/2] dt-bindings: soc: spacemit: k3: Decouple composite reset lines

[Yixun Lan]

Instead of grouping several different reset lines into one composite
reset, decouple them to individual ones which make it more aligned
with underlying hardware.

The DWC3 USB host controller in K3 SoC has three reset lines - AHB, VCC,
PHY. The PCIe controller also has three reset lines - DBI, Slave, Master.

Signed-off-by: Yixun Lan <dlan at kernel.org>
---
 include/dt-bindings/reset/spacemit,k3-resets.h | 42 ++++++++++++++++++++------
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
index 79ac1c22b7b5..c12f8bd32047 100644
--- a/include/dt-bindings/reset/spacemit,k3-resets.h
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -97,11 +97,7 @@
 #define RESET_APMU_SDH0          13
 #define RESET_APMU_SDH1          14
 #define RESET_APMU_SDH2          15
-#define RESET_APMU_USB2          16
-#define RESET_APMU_USB3_PORTA    17
-#define RESET_APMU_USB3_PORTB    18
-#define RESET_APMU_USB3_PORTC    19
-#define RESET_APMU_USB3_PORTD    20
+/* Deprecated USB 16 - 20 */
 #define RESET_APMU_QSPI          21
 #define RESET_APMU_QSPI_BUS      22
 #define RESET_APMU_DMA           23
@@ -143,16 +139,42 @@
 #define RESET_APMU_UFS_ACLK      59
 #define RESET_APMU_EDP0          60
 #define RESET_APMU_EDP1          61
-#define RESET_APMU_PCIE_PORTA    62
-#define RESET_APMU_PCIE_PORTB    63
-#define RESET_APMU_PCIE_PORTC    64
-#define RESET_APMU_PCIE_PORTD    65
-#define RESET_APMU_PCIE_PORTE    66
+/* Deprecated PCIe 62 - 66 */
 #define RESET_APMU_EMAC0         67
 #define RESET_APMU_EMAC1         68
 #define RESET_APMU_EMAC2         69
 #define RESET_APMU_ESPI_MCLK     70
 #define RESET_APMU_ESPI_SCLK     71
+#define RESET_APMU_USB2_AHB      72
+#define RESET_APMU_USB2_VCC      73
+#define RESET_APMU_USB2_PHY      74
+#define RESET_APMU_USB3_A_AHB    75
+#define RESET_APMU_USB3_A_VCC    76
+#define RESET_APMU_USB3_A_PHY    77
+#define RESET_APMU_USB3_B_AHB    78
+#define RESET_APMU_USB3_B_VCC    79
+#define RESET_APMU_USB3_B_PHY    80
+#define RESET_APMU_USB3_C_AHB    81
+#define RESET_APMU_USB3_C_VCC    82
+#define RESET_APMU_USB3_C_PHY    83
+#define RESET_APMU_USB3_D_AHB    84
+#define RESET_APMU_USB3_D_VCC    85
+#define RESET_APMU_USB3_D_PHY    86
+#define RESET_APMU_PCIE_A_DBI    87
+#define RESET_APMU_PCIE_A_SLAVE  88
+#define RESET_APMU_PCIE_A_MASTER 89
+#define RESET_APMU_PCIE_B_DBI    90
+#define RESET_APMU_PCIE_B_SLAVE  91
+#define RESET_APMU_PCIE_B_MASTER 92
+#define RESET_APMU_PCIE_C_DBI    93
+#define RESET_APMU_PCIE_C_SLAVE  94
+#define RESET_APMU_PCIE_C_MASTER 95
+#define RESET_APMU_PCIE_D_DBI    96
+#define RESET_APMU_PCIE_D_SLAVE  97
+#define RESET_APMU_PCIE_D_MASTER 98
+#define RESET_APMU_PCIE_E_DBI    99
+#define RESET_APMU_PCIE_E_SLAVE  100
+#define RESET_APMU_PCIE_E_MASTER 101
 
 /* DCIU resets*/
 #define RESET_DCIU_HDMA          0

-- 
2.53.0