[PATCH RFC 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM

[Junhui Liu]

Add support for the main CCU and the PRCM module (R-CCU) found in the
Allwinner A733 SoC. The clock architecture of the A733 is an evolution
of the previous A523 design but introduces several significant changes.

One of the key changes is the introduction of a "pll-ref" clock that
normalizes the physical oscillator frequency (which can be 19.2MHz,
24MHz, or 26MHz) into a consistent 24MHz reference for the entire clock
tree. Additionally, while the A733 inherits many module clock structures
from the A523, the MCU_CCU has been removed, and the overall clock tree
has been expanded to support more new functional units.

Also update the sunxi-ng SDM (Sigma-Delta Modulation) helper to support
a new dual-pattern register design. On the A733, the SDM enable bit has
been moved from the main PLL register to a second pattern register
(PATTERN1). The driver is updated to handle this register layout to
ensure accurate frequency synthesis for "pll-audio0".

This is marked as RFC because the parent clocks for several instances in
the main CCU are difficult to determine as the user manual provides
limited information on their specific clock sources. In these cases, the
implementation follows vendor practices and previous SoC designs,
generally defaulting to "hosc" where documentation is lacking. In
contrast, the bus clock gates in the PRCM (R-CCU) are explicitly defined
based on the Memory Map in the manual, which clearly associates each
module with its respective bus. Feedback or insights on these specific
clock parents would be greatly appreciated.

This functionally relies on the RTC series for the A733 SoC [1].

Link: https://lore.kernel.org/all/20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech/ [1]

---
Junhui Liu (8):
      dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
      clk: sunxi-ng: sdm: Add dual patterns support
      clk: sunxi-ng: a733: Add PRCM CCU
      clk: sunxi-ng: a733: Add PLL clocks support
      clk: sunxi-ng: a733: Add bus clocks support
      clk: sunxi-ng: a733: Add mod clocks support
      clk: sunxi-ng: a733: Add bus clock gates
      clk: sunxi-ng: a733: Add reset lines

 .../bindings/clock/allwinner,sun60i-a733-ccu.yaml  |  107 +
 drivers/clk/sunxi-ng/Kconfig                       |   10 +
 drivers/clk/sunxi-ng/Makefile                      |    4 +
 drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c           |  276 +++
 drivers/clk/sunxi-ng/ccu-sun60i-a733.c             | 2375 ++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu_sdm.c                     |   51 +-
 drivers/clk/sunxi-ng/ccu_sdm.h                     |   32 +-
 include/dt-bindings/clock/sun60i-a733-ccu.h        |  289 +++
 include/dt-bindings/clock/sun60i-a733-r-ccu.h      |   39 +
 include/dt-bindings/reset/sun60i-a733-ccu.h        |  131 ++
 include/dt-bindings/reset/sun60i-a733-r-ccu.h      |   23 +
 11 files changed, 3311 insertions(+), 26 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260202-a733-clk-0d4fc00a9f9c

Best regards,
-- 
Junhui Liu <junhui.liu at pigmoral.tech>