[PATCH v4 02/10] reset: eyeq: Add EyeQ7H compatibles

[Philipp Zabel]

On Mi, 2026-03-04 at 16:25 +0100, Benoît Monin wrote:
> Add support for the reset controllers found in the EyeQ7H OLB. For
> this, three new types of reset domain are added to the driver.
> 
> The EQR_EYEQ7H_ACRP reset domain is similar to the EQR_EYEQ5_ACRP domain,
> sharing the same register address calculation but featuring a different
> register layout. When writing to the register, MBIST bits are set to
> zero to ensure normal device operation.
> 
> The EQR_EYEQ7H_CFG reset domain is similar to the EQR_EYEQ5_PCIE domain,
> with two bits per device instead of one. These two bits, clock enable and
> nreset, are kept in sync when asserting and deasserting the device reset.
> 
> The EQR_EYEQ7H_ACC reset domain is similar to the EQR_EYEQ6H_SARCR domain,
> with a different registers layout and no busy waiting.
> 
> Alongside these new reset domains, add EQR_NB_DOM_TYPES at the end of the
> eqr_domain_type enumeration and use it to declare the eqr_timings array.
> This ensures that we have the expected number of entries when using the
> timings in eqr_busy_wait_locked().
> 
> Add and order the auxiliary_device_id entries in eqr_id_table.
> 
> Originally-by: Sari Khoury <sari.khoury at mobileye.com>
> Signed-off-by: Benoît Monin <benoit.monin at bootlin.com>

Reviewed-by: Philipp Zabel <p.zabel at pengutronix.de>

and, since this depends on patch 1,

Acked-by: Philipp Zabel <p.zabel at pengutronix.de>

to be merged with the rest of the series.

regards
Philipp