[RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output

Andrew Jones andrew.jones at oss.qualcomm.com
Fri Mar 6 10:34:57 PST 2026


On Fri, Mar 06, 2026 at 08:47:42PM +0800, Guodong Xu wrote:
> On Wed, Feb 25, 2026 at 8:08 AM Andrew Jones
> <andrew.jones at oss.qualcomm.com> wrote:
> >
> > On Sat, Feb 21, 2026 at 06:52:19PM +0800, Guodong Xu wrote:
> > > On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> > > <andrew.jones at oss.qualcomm.com> wrote:
> > > >
> > > > Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
> > > > new 'isa bases' lines both for the LCD of all harts and per hart, as
> > > > shown in the example output below when booting qemu with
> > > > -cpu rva23s64,sv39=on,pmp=on:
> > > >
> > > > processor       : 0
> > > > hart            : 4
> > > > isa bases       : rv64ima rva23u64
> > > > isa             : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > > > mmu             : sv39
> > > > mvendorid       : 0x0
> > > > marchid         : 0x0
> > > > mimpid          : 0x0
> > > > hart isa bases  : rv64ima rva23u64
> > > > hart isa        : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
> > > >
> > > > Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> > > > ---
> > > > +       /* RVA23S64 */
> > > > +       set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
> > > > +       /* TODO: Ss1p13 */
> > > > +       /* Svbare, Sv39 -- assumed */
> > > > +       set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
> > > > +       /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
> > >
> > > For this,
> > >
> > > > +       set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
> > > > +       set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
> > > > +       /* TODO: Ssu64xl */
> > > > +       /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */
> 
> Hi, drew
> 
> About 'Sha', your reading of the profile/spec, do you prefer to define
> Sha as a _BUNDLE or as a _SUPERSET() which has its own id?
> 
> I defined it as _SUPERSET() in my patch 8/8 [1], but with today's code
> review, I guess bundle is a better fit. What do you think?
> 
> BTW, Sha = H + 7 others. It includes H.

I agree a bundle is more suitable for Sha.

Thanks,
drew



More information about the linux-riscv mailing list