[PATCH v11 2/4] riscv: dts: qilai: Add PCIe node into the QiLai SoC

[Manivannan Sadhasivam]

On Wed, Feb 25, 2026 at 04:55:02PM +0800, Randolph wrote:
> From: Randolph Lin <randolph at andestech.com>
> 
> Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
> 
> Signed-off-by: Randolph Lin <randolph at andestech.com>

Acked-by: Manivannan Sadhasivam <mani at kernel.org>

One nit below.

> ---
>  arch/riscv/boot/dts/andes/qilai.dtsi | 109 +++++++++++++++++++++++++++
>  1 file changed, 109 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
> index de3de32f8c39..731ba12ccc95 100644
> --- a/arch/riscv/boot/dts/andes/qilai.dtsi
> +++ b/arch/riscv/boot/dts/andes/qilai.dtsi
> @@ -123,6 +123,7 @@ cpu3_intc: interrupt-controller {
>  	soc {
>  		compatible = "simple-bus";
>  		ranges;
> +		dma-ranges;
>  		interrupt-parent = <&plic>;
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> @@ -182,5 +183,113 @@ uart0: serial at 30300000 {
>  			reg-io-width = <4>;
>  			no-loopback-test;
>  		};
> +
> +		bus at 80000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
> +			ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
> +				 <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
> +				 <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
> +
> +			pcie at 80000000 {
> +				compatible = "andestech,qilai-pcie";
> +				device_type = "pci";
> +				reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
> +				      <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
> +				      <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */

No need to add comments about the register name space. You have reg-names below.

- Mani

> +				reg-names = "dbi", "apb", "config";
> +				dma-coherent;
> +
> +				linux,pci-domain = <0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
> +					 <0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;
> +
> +				#interrupt-cells = <1>;
> +				interrupts = <0xf 0x4>;
> +				interrupt-names = "msi";
> +				interrupt-parent = <&plic>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
> +						<0 0 0 2 &plic 0xf 0x4>,
> +						<0 0 0 3 &plic 0xf 0x4>,
> +						<0 0 0 4 &plic 0xf 0x4>;
> +			};
> +		};
> +
> +		bus at a0000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
> +			ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
> +				 <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
> +				 <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
> +
> +			pcie at a0000000 {
> +				compatible = "andestech,qilai-pcie";
> +				device_type = "pci";
> +				reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
> +				      <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
> +				      <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
> +				reg-names = "dbi", "apb", "config";
> +				dma-coherent;
> +
> +				linux,pci-domain = <1>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
> +					 <0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;
> +
> +				#interrupt-cells = <1>;
> +				interrupts = <0xe 0x4>;
> +				interrupt-names = "msi";
> +				interrupt-parent = <&plic>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
> +						<0 0 0 2 &plic 0xe 0x4>,
> +						<0 0 0 3 &plic 0xe 0x4>,
> +						<0 0 0 4 &plic 0xe 0x4>;
> +			};
> +		};
> +
> +		bus at c0000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
> +			ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
> +				 <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
> +				 <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
> +
> +			pcie at c0000000 {
> +				compatible = "andestech,qilai-pcie";
> +				device_type = "pci";
> +				reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
> +				      <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
> +				      <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
> +				reg-names = "dbi", "apb", "config";
> +				dma-coherent;
> +
> +				linux,pci-domain = <2>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
> +					 <0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;
> +
> +				#interrupt-cells = <1>;
> +				interrupts = <0xd 0x4>;
> +				interrupt-names = "msi";
> +				interrupt-parent = <&plic>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
> +						<0 0 0 2 &plic 0xd 0x4>,
> +						<0 0 0 3 &plic 0xd 0x4>,
> +						<0 0 0 4 &plic 0xd 0x4>;
> +			};
> +		};
>  	};
>  };
> -- 
> 2.34.1
> 

-- 
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