[RFC v11 1/4] gpio: mpfs: Add interrupt support

[Herve Codina]

Hi Conor,

On Fri, 27 Feb 2026 14:52:27 +0000
Conor Dooley <conor at kernel.org> wrote:

> From: Conor Dooley <conor.dooley at microchip.com>
> 
> Add support for interrupts to the PolarFire SoC GPIO driver. Each GPIO
> has an independent interrupt that is wired to an interrupt mux that sits
> between the controllers and the PLIC. The SoC has more GPIO lines than
> connections from the mux to the PLIC, so some GPIOs must share PLIC
> interrupts. The configuration is not static and is set at runtime,
> conventionally by the platform's firmware. CoreGPIO, the version
> intended for use in the FPGA fabric has two interrupt output ports, one
> is IO_NUM bits wide, as is used in the hardened cores, and the other is
> a single bit with all lines ORed together.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> Doing the chained thing kinda covers all the bases at the expense of the
> "direct" mode interrupts that have a dedicated connection to the PLIC.


Seems ok on my side.

Just a nitpick in probe().

Reviewed-by: Herve Codina <herve.codina at bootlin.com>

...
>  static int mpfs_gpio_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> +	struct device_node *node = pdev->dev.of_node;

dev->of_node instead of pdev->dev.of_node.

or move 'struct device_node *node = pdev->dev.of_node;' at first position
(reverse Xmas tree).

>  	struct mpfs_gpio_chip *mpfs_gpio;
> +	struct gpio_irq_chip *girq;

Best regards,
Hervé