[RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe

[Andrew Jones]

On Sat, Feb 21, 2026 at 06:50:25PM +0800, Guodong Xu wrote:
> On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
> <andrew.jones at oss.qualcomm.com> wrote:
> >
> > Ziccrse is already present in cpufeature.
> >
> > Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 16 ++++++++++++++++
> >  arch/riscv/include/asm/hwcap.h        |  3 +++
> >  arch/riscv/include/uapi/asm/hwprobe.h |  4 ++++
> >  arch/riscv/kernel/cpufeature.c        |  3 +++
> >  arch/riscv/kernel/sys_hwprobe.c       |  7 +++++--
> >  5 files changed, 31 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 4484f2a7f798..97226b7c5936 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -395,3 +395,19 @@ The following keys are defined:
> >  * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
> >    extensions that are compatible with the
> >    :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
> > +    as defined in the RISC-V Profiles specification starting from commit
> > +    b1d80660 ("Updated to ratified state.")
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index c17e11caca83..8e764dbc7413 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -112,6 +112,9 @@
> >  #define RISCV_ISA_EXT_ZILSD            102
> >  #define RISCV_ISA_EXT_ZCLSD            103
> >  #define RISCV_ISA_EXT_ZICCLSM          104
> > +#define RISCV_ISA_EXT_ZICCAMOA         105
> > +#define RISCV_ISA_EXT_ZICCIF           106
> > +#define RISCV_ISA_EXT_ZA64RS           107
> >
> >  #define RISCV_ISA_EXT_XLINUXENVCFG     127
> >
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 6a0163b54718..fed9ea6fd2b5 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -115,6 +115,10 @@ struct riscv_hwprobe {
> >  #define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0    14
> >  #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE    15
> >  #define RISCV_HWPROBE_KEY_IMA_EXT_1            16
> > +#define                RISCV_HWPROBE_EXT_ZICCAMOA      (1 << 0)
> > +#define                RISCV_HWPROBE_EXT_ZICCIF        (1 << 1)
> > +#define                RISCV_HWPROBE_EXT_ZICCRSE       (1 << 2)
> > +#define                RISCV_HWPROBE_EXT_ZA64RS        (1 << 3)
> >  /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
> >
> >  /* Flags */
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index ca7a34f66738..b001e78eecf6 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -488,6 +488,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> >         __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
> >         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
> > +       __RISCV_ISA_EXT_DATA(ziccamoa, RISCV_ISA_EXT_ZICCAMOA),
> 
> It might be good to also enforce extension dependencies here:
> Za64rs depends on Zalrsc, and Ziccamoa depends on Zaamo.

There's certainly a practical "dependency". Za64rs wouldn't make much
sense to support without instructions that need a reservation set. And
similarly Ziccamoa doesn't make much sense without Zaamo. However, I'm not
aware of anything that explicitly states Ziccamoa implies Zaamo or Za64rs
implies Zalrsc. So, in the absence of any rules, I vote we leave them
independent.

Thanks,
drew