[RFC PATCH v1 04/11] riscv: Add B to hwcap

[Guodong Xu]

Hi, Drew

On Fri, Feb 6, 2026 at 8:24 AM Andrew Jones
<andrew.jones at oss.qualcomm.com> wrote:
>
> Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs
> are all set.
>
> Signed-off-by: Andrew Jones <andrew.jones at oss.qualcomm.com>
> ---
>  arch/riscv/include/asm/hwcap.h      | 1 +
>  arch/riscv/include/uapi/asm/hwcap.h | 1 +
>  arch/riscv/kernel/cpufeature.c      | 8 ++++++++
>  3 files changed, 10 insertions(+)

I saw you chose not to add B to hwprobe in this series, per
your review of my patch [1]. I have a different opinion.

As you said, FD, C, and V are all exported through both hwcap
and hwprobe. Adding B to hwprobe too keeps things consistent,
users can query all the single-letter extensions from one
interface without needing to know that B is missing in hwprobe
and that they'd have to check Zba/Zbb/Zbs to infer B support.

Relying on the rva23u64 base bit to imply B also doesn't cover
chips that implement B without being rva23u64 compliant. Eg. my
patchset [2] adds support for existing (non-rva23u64) SoCs.

Link: https://lore.kernel.org/all/k3riksgjci3jw7tgqf27tu6vrfxfs6e7jo5jinwwadyruyqgb6@apqyim4zdcqc/
[1]
Link: https://lore.kernel.org/all/20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com/
[2]

Thanks,
Guodong



Guodong

>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 03acd22bbbaa..c17e11caca83 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -11,6 +11,7 @@
>  #include <uapi/asm/hwcap.h>
>
>  #define RISCV_ISA_EXT_A                ('a' - 'a')
> +#define RISCV_ISA_EXT_B                ('b' - 'a')
>  #define RISCV_ISA_EXT_C                ('c' - 'a')
>  #define RISCV_ISA_EXT_D                ('d' - 'a')
>  #define RISCV_ISA_EXT_F                ('f' - 'a')
> diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
> index c52bb7bbbabe..96b7cf854e09 100644
> --- a/arch/riscv/include/uapi/asm/hwcap.h
> +++ b/arch/riscv/include/uapi/asm/hwcap.h
> @@ -21,6 +21,7 @@
>  #define COMPAT_HWCAP_ISA_F     (1 << ('F' - 'A'))
>  #define COMPAT_HWCAP_ISA_D     (1 << ('D' - 'A'))
>  #define COMPAT_HWCAP_ISA_C     (1 << ('C' - 'A'))
> +#define COMPAT_HWCAP_ISA_B     (1 << ('B' - 'A'))
>  #define COMPAT_HWCAP_ISA_V     (1 << ('V' - 'A'))
>
>  #endif /* _UAPI_ASM_RISCV_HWCAP_H */
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 25ed1d6958d7..ca7a34f66738 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -429,6 +429,12 @@ static const unsigned int riscv_c_exts[] = {
>         RISCV_ISA_EXT_ZCD,
>  };
>
> +static const unsigned int riscv_b_exts[] = {
> +       RISCV_ISA_EXT_ZBA,
> +       RISCV_ISA_EXT_ZBB,
> +       RISCV_ISA_EXT_ZBS,
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -476,6 +482,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>         __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_D, riscv_ext_d_validate),
>         __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
>         __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
> +       __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts, riscv_ext_vector_float_validate),
>         __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),
>         __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> @@ -1089,6 +1096,7 @@ void __init riscv_fill_hwcap(void)
>         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
>         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
>         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
> +       isa2hwcap['b' - 'a'] = COMPAT_HWCAP_ISA_B;
>         isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
>
>         if (!acpi_disabled) {
> --
> 2.43.0
>