[PATCH 1/5] dmaengine: sf-pdma: add missing PDMA base offset to register calculations

[Frank Li]

On Sat, Feb 21, 2026 at 03:43:53AM +0800, Max Hsu wrote:
> The PDMA control registers start at offset 0x80000 from the PDMA base
> address, according to the FU540-C000 v1p1 manual [1].
>
> The current SF_PDMA_REG_BASE macro is missing this offset:
>     Current:  pdma->membase + (PDMA_CHAN_OFFSET * ch)
>     Correct:  pdma->membase + 0x80000 + (PDMA_CHAN_OFFSET * ch)

How it work at previous version? suppose it is tested when upstream this
driver?

>
> Fix by adding PDMA_BASE_OFFSET (0x80000) to the register address
> calculation.
>
> Link: https://www.sifive.com/document-file/freedom-u540-c000-manual [1]
> Fixes: 6973886ad58e ("dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00")
> Signed-off-by: Max Hsu <max.hsu at sifive.com>
> ---
>  drivers/dma/sf-pdma/sf-pdma.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h
> index 215e07183d7e..d33551eb2ee8 100644
> --- a/drivers/dma/sf-pdma/sf-pdma.h
> +++ b/drivers/dma/sf-pdma/sf-pdma.h
> @@ -24,7 +24,7 @@
>
>  #define PDMA_MAX_NR_CH					4
>
> -#define PDMA_BASE_ADDR					0x3000000

This change belong to cleanup, don't mix to fixes into fix patch.

> +#define PDMA_BASE_OFFSET				0x80000
>  #define PDMA_CHAN_OFFSET				0x1000
>
>  /* Register Offset */
> @@ -54,7 +54,7 @@
>  /* Error Recovery */
>  #define MAX_RETRY					1
>
> -#define SF_PDMA_REG_BASE(ch)	(pdma->membase + (PDMA_CHAN_OFFSET * (ch)))
> +#define SF_PDMA_REG_BASE(ch)	(pdma->membase + PDMA_BASE_OFFSET + (PDMA_CHAN_OFFSET * (ch)))

why not set membase to pdma->membase + PDMA_BASE_OFFSET directly? are there
registers between pdma->membase and pdma->membase + PDMA_BASE_OFFSET?

Frank

>
>  struct pdma_regs {
>  	/* read-write regs */
>
> --
> 2.43.0
>