[PATCH v2 0/2] riscv: Introduce support for hardware break/watchpoints

[Himanshu Chauhan]

On Fri, Feb 13, 2026 at 6:04 AM Paul Walmsley <pjw at kernel.org> wrote:
>
> Hi Himanshu,
>
> On Tue, 6 Jan 2026, Himanshu Chauhan wrote:
>
> > This patchset adds support of hardware breakpoints and watchpoints in RISC-V
> > architecture. The framework is built on top of perf subsystem and SBI debug
> > trigger extension.
> >
> > Currently following features are not supported and are in works:
> >  - Ptrace support
> >  - Single stepping
> >  - Virtualization of debug triggers
> >
> > The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification:
> > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf
> >
> > The Sdtrig ISA is part of RISC-V debug specification which can be found at:
> > https://github.com/riscv/riscv-debug-spec
>
> Can you fix the checkpatch issues with this series?  Please use --strict.
>
> In the meantime, I'll add it as an experimental branch, until those get
> sorted out.
>
Sure. I will do that.

Regards
Himanshu
>
> - Paul