[PATCH 1/8] riscv: cpufeature: Add parsing for B

[Guodong Xu]

Hi Drew,

On Mon, Feb 9, 2026 at 12:43 AM Andrew Jones
<andrew.jones at oss.qualcomm.com> wrote:
>
> On Sat, Feb 07, 2026 at 06:27:55PM +0800, Guodong Xu wrote:
> > The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
> > by version 20240411 of the RISC-V Instruction Set Manual Volume I
> > Unprivileged Architecture.
> >
> > Add B as a superset extension so that when "b" is encountered in the ISA
> > string or devicetree, its sub-extensions are automatically enabled.
> >
> > Signed-off-by: Guodong Xu <guodong at riscstar.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  1 +
> >  arch/riscv/kernel/cpufeature.c | 10 ++++++++++
> >  2 files changed, 11 insertions(+)
> >

>
> Hi Guodong Xu,
>
> As part of the "hwprobe: Introduce rva23u64 base behavior" RFC [1] I

Thanks for pointing me to your link. I'm happy to look
at your RFC series. I like your part of adding rva23u64
and rva23s64, I've been thinking the same, but you
offered the solution!

> posted a similar patch where I also added B to hwcap. Can you take a
> look at that?

Sure, I'll comment in your series.

>
> [1] https://lore.kernel.org/all/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/

With the patches in [1], I would drop the duplicated
ones from my series (5 of them if I counted correctly),
and keep only the 3 patches which add SHA and other
S extensions.

Would you prefer I send a v2 based on your series, or
would it be easier for you to pick them up directly?
Either way works for me.

Best regards,
Guodong Xu

>
> Thanks,
> drew