[External] [PATCH RFC v2 03/17] RISC-V: Add support for srmcfg CSR from Ssqosid ext

[Drew Fustini]

On Mon, Feb 02, 2026 at 11:17:52AM +0800, yunhui cui wrote:
> Hi Drew,
> 
> On Thu, Jan 29, 2026 at 4:28 AM Drew Fustini <fustini at kernel.org> wrote:
> >
> > Add support for the srmcfg CSR defined in the Ssqosid ISA extension
> > (Supervisor-mode Quality of Service ID). The CSR contains two fields:
> >
> >   - Resource Control ID (RCID) used determine resource allocation
> >   - Monitoring Counter ID (MCID) used to track resource usage
> >
> > Requests from a hart to shared resources like cache will be tagged with
> > these IDs. This allows the usage of shared resources to be associated
> > with the task currently running on the hart.
> >
> > A srmcfg field is added to thread_struct and has the same format as the
> > srmcfg CSR. This allows the scheduler to set the hart's srmcfg CSR to
> > contain the RCID and MCID for the task that is being scheduled in. The
> > srmcfg CSR is only written to if the thread_struct.srmcfg is different
> > than the current value of the CSR.
> >
> > A per-cpu variable cpu_srmcfg is used to mirror that state of the CSR.
> > This is because access to L1D hot memory should be several times faster
> > than a CSR read. Also, in the case of virtualization, accesses to this
> > CSR are trapped in the hypervisor.
> >
> > Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
> > Co-developed-by: Kornel Dulęba <mindal at semihalf.com>
> > Signed-off-by: Kornel Dulęba <mindal at semihalf.com>
> > [fustini: rename csr, refactor switch_to, rebase on upstream]
> > Signed-off-by: Drew Fustini <fustini at kernel.org>
[..]
> > diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h
> > new file mode 100644
> > index 000000000000..84830d7c6dc4
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/qos.h
> > @@ -0,0 +1,41 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef _ASM_RISCV_QOS_H
> > +#define _ASM_RISCV_QOS_H
> > +
> > +#ifdef CONFIG_RISCV_ISA_SSQOSID
> > +
> > +#include <linux/sched.h>
> > +#include <linux/jump_label.h>
> > +
> > +#include <asm/barrier.h>
> > +#include <asm/csr.h>
> > +#include <asm/hwcap.h>
> > +
> > +/* cached value of srmcfg csr for each cpu */
> > +DECLARE_PER_CPU(u32, cpu_srmcfg);
> > +
> > +static inline void __switch_to_srmcfg(struct task_struct *next)
> > +{
> > +       u32 *cpu_srmcfg_ptr = this_cpu_ptr(&cpu_srmcfg);
> > +       u32 thread_srmcfg;
> > +
> > +       thread_srmcfg = READ_ONCE(next->thread.srmcfg);
> 
> 
> First set the cpu_list, and then the condition thread_srmcfg !=
> *cpu_srmcfg_ptr will not be satisfied. Is a default value required
> here? Both code paths for cpu_list and tasks are compared against the
> default value; you may refer to the implementation of mpam.

I'm having trouble finding cpu_list but I think that it does make sense
to set the initial value.

Were you thinking I should look at mpam_set_cpu_defaults() in
the mpam_resctrl_glue_v4 [1] branch?

Thanks,
Drew

[1] https://gitlab.arm.com/linux-arm/linux-bh.git