[PATCH V2] crypto: aegis128: Add RISC-V vector SIMD implementation

[Herbert Xu]

On Mon, Jan 26, 2026 at 05:24:11PM +0800, Chunyan Zhang wrote:
> Add a RISC-V vector-accelerated implementation of aegis128 by
> wiring it into the generic SIMD hooks.
> 
> This implementation supports vlen values of 512, 256, and 128.
> 
> Signed-off-by: Chunyan Zhang <zhangchunyan at iscas.ac.cn>
> ---
> V2:
> - Add config dependency of RISCV_ISA_V to fix the issue reported by kernel test robot;
> - Add return value in preload_round_data() and aegis128_round().
> 
> V1: https://lore.kernel.org/all/20260121101923.64657-1-zhangchunyan@iscas.ac.cn/
> ---
>  crypto/Kconfig              |   4 +-
>  crypto/Makefile             |   4 +
>  crypto/aegis-rvv.h          |  19 +
>  crypto/aegis128-rvv-inner.c | 762 ++++++++++++++++++++++++++++++++++++
>  crypto/aegis128-rvv.c       |  63 +++
>  5 files changed, 850 insertions(+), 2 deletions(-)
>  create mode 100644 crypto/aegis-rvv.h
>  create mode 100644 crypto/aegis128-rvv-inner.c
>  create mode 100644 crypto/aegis128-rvv.c

In light of the recent move of aes from crypto to lib/crypto,
perhaps the same should be done for aegis?

Thanks,
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt