[PATCH v3 3/8] iommu/riscv: Add HPM support for performance monitoring

[Lv Zheng]

On 2/5/2026 11:47 AM, Zong Li wrote:
> On Thu, Feb 5, 2026 at 11:35 AM Lv Zheng <lv.zheng at linux.spacemit.com> wrote:
>>
>> On 2/5/2026 2:39 AM, Andrew Jones wrote:
>>> How does this relate to
>>>
>>> https://lore.kernel.org/all/20250115030306.29735-1-zong.li@sifive.com/
>>>
>>>   From a quick skim it looks like there's plenty of overlap.
>>
>> We developed the driver in 2024 and demonstrated it in China summit. We
>> didn't notice that a patch is on-going now in the community.
>>
>> Now it looks our approach solved more issues, and we'll check and update
>> if there are any community concerns still not addressed in this patchset.
>>
>> We can add Reviewed-by/Tested-by and Signed-off-by of Zong Li to this
>> patch if he wishes.
>>
>> Thanks,
>> Lv
>>
> 
> Perhaps I can first post my next revision to the mailing list (hope it
> won't waste the community resource), so that you could have a chance
> to review it and see whether that version is architecturally closer to
> what the community is looking for, while also addressing your issue.
> If you also feel that my next revision meets your needs, perhaps you
> could append your additional implementations on top of it.
>

It seems we all composed the RISC-V iommu HPM support by referencing 
drivers/perf/arm_smmuv3_pmu.

Robin's comments should all be addressed IMHO.

> Of course, if the community would prefer to go your version, I’m
> perfectly fine with that as well.

OK. If we send a next version, we will add your SOB and please help to 
review and test.

Thanks in advance,
Lv

> 
>>>
>>> Thanks,
>>> drew
>>>
>>>
>>> On Wed, Feb 04, 2026 at 05:09:01PM +0800, Lv Zheng wrote:
>>>> From: Jingyu Li <joey.li at spacemit.com>
>>>>
>>>> Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance
>>>> monitoring capabilities.
>>>>
>>>> Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static
>>>> counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter
>>>> indexes of other HPMEVENTS in order to correctly index into IOHPMEVT and
>>>> IOHPMCTR registers that have already been defined in the iommu-bits.h.
>>>> However the users treat 0 as the index of HPMCYCLES and 1~COUNTER_MAX-1 as
>>>> the indexes of other HPMEVENTS, thus care should be taken in dealing with
>>>> counter indexes between userspace and kernel space.
>>>>
>>>> Signed-off-by: Jingyu Li <joey.li at spacemit.com>
>>>> Signed-off-by: Lv Zheng <lv.zheng at linux.spacemit.com>
>>>> Link: https://github.com/riscv-non-isa/riscv-iommu
>>>> ---
>>>>    drivers/iommu/riscv/Kconfig          |   9 +
>>>>    drivers/iommu/riscv/Makefile         |   1 +
>>>>    drivers/iommu/riscv/iommu-bits.h     |   6 +
>>>>    drivers/iommu/riscv/iommu-hpm.c      | 843 +++++++++++++++++++++++++++
>>>>    drivers/iommu/riscv/iommu-pci.c      |  13 +-
>>>>    drivers/iommu/riscv/iommu-platform.c |   8 +-
>>>>    drivers/iommu/riscv/iommu.h          |  42 ++
>>>>    7 files changed, 919 insertions(+), 3 deletions(-)
>>>>    create mode 100644 drivers/iommu/riscv/iommu-hpm.c
>>>>
>>>
>>
>