[PATCH v3 4/8] dt-bindings: iommu: Add spacemit/t100 features

[Lv Zheng]

On 2/5/2026 1:37 AM, Conor Dooley wrote:
> On Wed, Feb 04, 2026 at 05:09:12PM +0800, Lv Zheng wrote:
>> Adds device tree bindings for SpacemiT T100 specific features by
>> introducing spacemit,100 compatible. T100 contains distributed IOATCs,
>> each of which exposes pmiv interrupt.
>>
>> Signed-off-by: Lv Zheng <lv.zheng at linux.spacemit.com>
>> Signed-off-by: Jingyu Li <joey.li at spacemit.com>
>> ---
>>   .../bindings/iommu/riscv,iommu.yaml           | 37 +++++++++++++++++++
>>   1 file changed, 37 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
>> index d4838c3b3741..2da3456e7402 100644
>> --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
>> @@ -32,6 +32,12 @@ properties:
>>     # should be specified along with 'reg' property providing MMIO location.
>>     compatible:
>>       oneOf:
>> +      - description: SpacemiT distributed IOMMUs
>> +        items:
>> +          - enum:
>> +              - spacemit,t100
>> +          - const: spacemit,riscv-iommu
> 
> What actually is the t100? Is it an SoC or is it the name of the core
> complex IP that spacemit is using in multiple SoCs?

T100 is the name of the IOMMU IP developed by SpacemiT, announced in 
RISC-V 2024 China Summit:
https://www.bilibili.com/video/BV1DNtCeiEBk/
It's world first server SPEC IOMMU in RISC-V, supports IOTLB placed in 
adjacent to the DMA masters and supports PCIe ATS and PRI.
You can find it shipped in the recent publicly purchasable SoC SpacemiT K3.

> 
>> +          - const: riscv,iommu
>>         - items:
>>             - enum:
>>                 - qemu,riscv-iommu
>> @@ -75,6 +81,23 @@ required:
>>   
>>   additionalProperties: false
>>   
>> +select: false
> 
> Why is this here? It just breaks the whole binding.
> pw-bot: changes-requested

OK.

> 
>> +
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: spacemit,riscv-iommu
>> +    then:
>> +      properties:
>> +        interrupts:
>> +          maxItems: 68
> 
> This isn't right. You would need to make the interrupts property itself
> have maxItems: 68, then add an else to this conditional that has
> maxItems: 4. What you've done just doesn't work, and if you removed the
> "select: false: you'd see.

Indeed, thanks for pointing this out.
Will dig deeper to correct this.

> 
>> +          description:
>> +            SpacemiT distributed IOMMU includes additional interrupts for
>> +            IOATCs. Each IOATC exposes pmiv wired vector as standalone
>> +            interrupt and the maximum number of IOATCs can be up to 64.
>> +
>>   examples:
>>     - |+
>>       /* Example 1 (IOMMU device with wired interrupts) */
>> @@ -145,3 +168,17 @@ examples:
>>               };
>>           };
>>       };
>> +
>> +  - |+
>> +    /* Example 5 (SpacemiT distributed IOMMU) */
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    iommu4: iommu at 1bccd000 {
> 
> Remove the iommu4 label, there's no references to it.

Sure.

Cheers,
Lv

> 
> Cheers,
> Conor.
> 
>> +        compatible = "spacemit,t100", "spacemit,riscv-iommu", "riscv,iommu";
>> +        reg = <0x1bccd000 0x1000>;
>> +        interrupts = <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <58 IRQ_TYPE_LEVEL_HIGH>, <58 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-parent = <&saplic>;
>> +        #iommu-cells = <0x01>;
>> +    };
>> -- 
>> 2.43.0
>>