[PATCH v2 4/6] reset: anlogic: add support for Anlogic DR1V90 resets

[Philipp Zabel]

On So, 2025-10-26 at 22:00 +0800, Junhui Liu wrote:
> Add reset controller support for the Anlogic DR1V90 SoC, which is an
> auxiliary device associated with the Clock and Reset Unit (CRU). All
> resets are active-low.
> 
> Signed-off-by: Junhui Liu <junhui.liu at pigmoral.tech>
> ---
>  drivers/reset/Kconfig        |   9 +++
>  drivers/reset/Makefile       |   1 +
>  drivers/reset/reset-dr1v90.c | 135 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 145 insertions(+)
> 
[...]
> diff --git a/drivers/reset/reset-dr1v90.c b/drivers/reset/reset-dr1v90.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..eb9064e3ab454fb39adc1ad426f458e39bb6169e
> --- /dev/null
> +++ b/drivers/reset/reset-dr1v90.c
> @@ -0,0 +1,135 @@
[...]
> +static const struct dr1v90_reset_map dr1v90_resets[] = {
> +	[RESET_OCM]		= { 0x74, BIT(4)},
[...]
> +	[RESET_NIC_HP0]		= { 0x78, BIT(0)},
[...]
> +	[RESET_USB0]		= { 0x7C, BIT(0)},

The registers 0x74, 0x78, and 0x7C are exclusively used for resets?

[...]
> +};
> +
> +static int dr1v90_reset_control_update(struct reset_controller_dev *rcdev,
> +				       unsigned long id, bool assert)
> +{
> +	struct dr1v90_reset_controller *rstc = to_dr1v90_reset_controller(rcdev);
> +	u32 offset = dr1v90_resets[id].offset;
> +	u32 bit = dr1v90_resets[id].bit;
> +	u32 reg;
> +
> +	reg = readl(rstc->base + offset);
> +	if (assert)
> +		reg &= ~bit;
> +	else
> +		reg |= bit;
> +	writel(reg, rstc->base + offset);

There should be a lock around this read-modify-write access.

regards
Philipp