[PATCH v2 0/6] clk/reset: anlogic: add support for DR1V90 SoC

[Troy Mitchell]

On Sun, Oct 26, 2025 at 10:00:40PM +0800, Junhui Liu wrote:
> This adds Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC,
> as well as corresponding dts bindings and dts integration.
> 
> The CRU driver framework is built around the clock controller as the
> primary device, with the reset controller implemented as an auxiliary
> device. The clock part refers to the vendor's code [1] to determine the
> structure of the clock tree.
> 
> The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
> UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
> core). Most of the clock tree and CRU design can be shared between them.
> This series only adds CRU support for DR1V90. Nevertheless, the driver
> is structured to make future extension to other DR1 variants like
> DR1M90.
> 
> This depends on the basic dt series for DR1V90 SoC [2].
> 
> Link: https://gitee.com/anlogic/linux/blob/anlogic-6.1.54/drivers/clk/anlogic/anl_dr1x90_crp.c [1]
> Link: https://lore.kernel.org/all/20251021-dr1v90-basic-dt-v3-0-5478db4f664a@pigmoral.tech/ [2]
> ---
Do we really need a cover-letter? Since you only have one patch, Is it
better to put the above information below the --- line in the actual patch?

                                      - Troy