[PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries

[Radim Krčmář]

2025-10-21T16:31:05+08:00, Hui Min Mina Chou <minachou at andestech.com>:
> From: Hui Min Mina Chou <minachou at andestech.com>
>
> If multiple VCPUs of the same Guest/VM run on the same Host CPU,
> hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
> may retain stale VS-stage entries. When a VCPU later migrates to a
> different Host CPU, it can hit these stale GVA to GPA mappings, causing
> unexpected faults in the Guest.
>
> To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
> G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
> This ensures that no stale VS-stage mappings remain after VCPU migration.
>
> Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CPU changes")
> Signed-off-by: Hui Min Mina Chou <minachou at andestech.com>
> Signed-off-by: Ben Zong-You Xie <ben717 at andestech.com>
> ---

The vvma flush is not necessary on implementation that have a single TLB
for the combined mapping, but there is no good way of detecting that,

Reviewed-by: Radim Krčmář <rkrcmar at ventanamicro.com>