[GIT PULL] RISC-V Tenstorrent Devicetree for v6.19
Drew Fustini
fustini at kernel.org
Sun Oct 19 10:23:37 PDT 2025
Hi Arnd,
Please pull these changes which add Tenstorrent as a vendor and enable
support for Blackhole. It adds the appropriate entries in MAINTAINERS.
The changes all come from a single series [1] posted by myself. Joel
Stanley has reviewed and tested all the patches. Rob acked or reviewed
all the bindings patches. W=1 dtbs_check and dt_binding_check produce
no warnings.
[1] https://lore.kernel.org/linux-riscv/20251013-tt-bh-dts-v3-0-9f058d4bbbda@oss.tenstorrent.com/
Thanks,
Drew
The following changes since commit 3a8660878839faadb4f1a6dd72c3179c1df56787:
Linux 6.18-rc1 (2025-10-12 13:42:36 -0700)
are available in the Git repository at:
git at github.com:tenstorrent/linux.git tags/tenstorrent-dt-for-v6.19
for you to fetch changes up to a71e6e8eea8ae2d624f097911f43357bba06d2a5:
riscv: defconfig: Enable Tenstorrent SoCs (2025-10-18 10:44:15 -0700)
----------------------------------------------------------------
Tenstorrent device tree for v6.19
Add Tenstorrent as a vendor and enable support for the Blackhole SoC
in Blackhole P100 and P150 PCIe cards. The SoC contains four RISC-V
CPU tiles consisting of 4x SiFive X280 cores.
There is a virtual UART implemented in OpenSBI firmware that allows a
console program on the PCIe host to communicate through shared memory
with Linux running on the Blackhole card.
Link: https://github.com/tenstorrent/tt-bh-linux
Link: https://github.com/tenstorrent/opensbi/
Signed-off-by: Drew Fustini <fustini at kernel.org>
----------------------------------------------------------------
Drew Fustini (8):
dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC
dt-bindings: riscv: Add Tenstorrent Blackhole compatible
dt-bindings: riscv: cpus: Add SiFive X280 compatible
dt-bindings: timers: Add Tenstorrent Blackhole compatible
dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards
riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs
riscv: defconfig: Enable Tenstorrent SoCs
.../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/tenstorrent.yaml | 28 ++++++
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 9 ++
arch/riscv/Kconfig.socs | 8 ++
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/tenstorrent/Makefile | 2 +
arch/riscv/boot/dts/tenstorrent/blackhole-card.dts | 14 +++
arch/riscv/boot/dts/tenstorrent/blackhole.dtsi | 108 +++++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
12 files changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/tenstorrent.yaml
create mode 100644 arch/riscv/boot/dts/tenstorrent/Makefile
create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole-card.dts
create mode 100644 arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
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