[PATCH v3 3/8] dt-bindings: riscv: cpus: Add SiFive X280 compatible

[Drew Fustini]

From: Drew Fustini <dfustini at oss.tenstorrent.com>

Document compatible for the SiFive X280 RISC-V core.

Acked-by: Rob Herring (Arm) <robh at kernel.org>
Reviewed-by: Joel Stanley <jms at oss.tenstorrent.com>
Signed-off-by: Drew Fustini <dfustini at oss.tenstorrent.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 153d0dac57fb39d39219e138792f4cb831cb88dc..afb8533f6a081bd9b91e13e30185f99ec2d5dc3b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -70,6 +70,7 @@ properties:
           - enum:
               - sifive,e51
               - sifive,u54-mc
+              - sifive,x280
           - const: sifive,rocket0
           - const: riscv
       - const: riscv    # Simulator only

-- 
2.34.1