[PATCH v2 0/4] riscv: hwprobe: Add Zicbop support
Yao Zihong
zihong.plct at isrc.iscas.ac.cn
Thu Oct 9 06:41:50 PDT 2025
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Changes since v1:
------------------
- Bump RISCV_HWPROBE_MAX_KEY (modified 1/4).
- Add documentation for the Zicbop hwprobe bit/key (new 3/4).
- Add a selftest(prefetch.c) for Zicbop (new 4/4).
Add UAPI and kernel plumbing to expose the Zicbop extension presence
and its block size through hwprobe. The interface mirrors
Zicbom/Zicboz. This allows userspace to safely discover and optimize
for Zicbop when available.
Background: Zicbop is mandated by the RVA22U64 profile. Downstream may
combine the presence bit with ZICBOP_BLOCK_SIZE to make profile-level
policy decisions or enable Zicbop-specific optimizations.
Yao Zihong (4):
uapi: riscv: hwprobe: Add Zicbop extension bit and block-size key
riscv: hwprobe: Report Zicbop presence and block size
docs: riscv: Document hwprobe for Zicbop
selftests/riscv: Add Zicbop prefetch test
Documentation/arch/riscv/hwprobe.rst | 8 +-
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 +
arch/riscv/kernel/sys_hwprobe.c | 6 +
.../testing/selftests/riscv/hwprobe/Makefile | 5 +-
.../selftests/riscv/hwprobe/prefetch.c | 236 ++++++++++++++++++
6 files changed, 256 insertions(+), 3 deletions(-)
create mode 100644 tools/testing/selftests/riscv/hwprobe/prefetch.c
--
2.47.2
- Previous message (by thread): [PATCH RESEND 28/62] init: alpha, arc, arm, arm64, csky, m68k, microblaze, mips, nios2, openrisc, parisc, powerpc, s390, sh, sparc, um, x86, xtensa: rename initrd_{start,end} to virt_external_initramfs_{start,end}
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