[PATCH v7 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Yao Zi]

On Tue, Jul 29, 2025 at 01:58:12PM +0800, Ze Huang wrote:
> On Tue, Jul 29, 2025 at 01:41:01AM +0000, Yao Zi wrote:
> > On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote:
> > > Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> > > in the SpacemiT K1 SoC. The controller is based on the Synopsys
> > > DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> > > DRD mode.
> > > 
> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> > > Signed-off-by: Ze Huang <huang.ze at linux.dev>
> > > ---
> > >  .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 124 +++++++++++++++++++++
> > >  1 file changed, 124 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > new file mode 100644
> > > index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> > > @@ -0,0 +1,124 @@
> > 
> > ...
> > 
> > > +  resets:
> > > +    items:
> > > +      - description: USB3.0 AHB reset
> > > +      - description: USB3.0 VCC reset
> > > +      - description: USB3.0 PHY reset
> > > +      - description: PCIE0 global reset (for combo phy)
> > 
> > Why should the USB driver takes care of the PCIe stuff? This sounds
> > strange to me.
> > 
> 
> On K1, PHY depends on the clocks and resets it shares with the controller,
> and the controller driver is guarantees that any needed clocks are enabled,
> and any resets that affect the PHY are de-asserted before using the PHY.

So does the "PCIe0 global reset" make effects to both USB3 and PCIe
**controllers**? If not, this is something wrong in the devicetree side.

> RESET_PCIE0_GLOBAL reset is necessary during, and only, the calibration stage
> of combo phy.

If it's only used by PHY, why couldn't it be a property of the PHY?
Sorry, but I still cannot get the point.

Regards,
Yao Zi

> To simplify both the driver architecture and the device tree files,
> RESET_PCIE0_GLOBAL (and some other clk/reset) are now managed by the
> relevant controller driver (either USB3 or PCIe0) instead of PHY driver.
> 
> Only one of USB3.0 SuperSpeed and PCIe-0 will be activated in a boot.
> PCIe-0 will not be affected when it's working.