[PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC device tree

[Conor Dooley]

On Mon, Jul 21, 2025 at 11:46:14PM +0800, Junhui Liu wrote:
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <800000000>;
> +
> +		cpu at 0 {
> +			compatible = "nuclei,ux900", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			riscv,isa = "rv64imafdc";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
> +					       "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
> +					       "zihintpause", "zihpm";

Why do riscv,isa and riscv,isa-extensions differ?
If riscv,isa is not even accurate, why not just remove it entirely?

> +			i-cache-block-size = <64>;
> +			i-cache-size = <32768>;
> +			i-cache-sets = <256>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <32768>;
> +			d-cache-sets = <256>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
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