[PATCH v3 3/9] RISC-V: KVM: Add support for Raw event v2
Anup Patel
anup at brainfault.org
Thu Jul 17 08:18:58 PDT 2025
On Fri, May 23, 2025 at 12:33 AM Atish Patra <atishp at rivosinc.com> wrote:
>
> SBI v3.0 introuced a new raw event type v2 for wider mhpmeventX
s/introuced/introduced/
> programming. Add the support in kvm for that.
>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> ---
> arch/riscv/kvm/vcpu_pmu.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 78ac3216a54d..15d71a7b75ba 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -60,6 +60,7 @@ static u32 kvm_pmu_get_perf_event_type(unsigned long eidx)
> type = PERF_TYPE_HW_CACHE;
> break;
> case SBI_PMU_EVENT_TYPE_RAW:
> + case SBI_PMU_EVENT_TYPE_RAW_V2:
> case SBI_PMU_EVENT_TYPE_FW:
> type = PERF_TYPE_RAW;
> break;
> @@ -128,6 +129,9 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data)
> case SBI_PMU_EVENT_TYPE_RAW:
> config = evt_data & RISCV_PMU_RAW_EVENT_MASK;
> break;
> + case SBI_PMU_EVENT_TYPE_RAW_V2:
> + config = evt_data & RISCV_PMU_RAW_EVENT_V2_MASK;
> + break;
> case SBI_PMU_EVENT_TYPE_FW:
> if (ecode < SBI_PMU_FW_MAX)
> config = (1ULL << 63) | ecode;
>
> --
> 2.43.0
>
Otherwise, it looks good to me.
Reviewed-by: Anup Patel <anup at brainfault.org>
Regards,
Anup
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