[WIP] RISC-V: Add the mising clobbers while probing vector misaligned access

[Palmer Dabbelt]

There was a comment left behind in
check_vector_unaligned_access_emulated() describing the need for a
clobber in the asm block we're using to probe for vector misaligned
access support.  This only mentions V0, but we should clobber whatever
that vsetvli clobbers as well.  That all likely requires poking through
the compilers and figuring out which clobbers are legal in which
configurations, so I'm sending this as a WIP for now.

I doubt it's possible to actually manifest this as a bug in practice, as
we'd need the compiler to generate some vector code in a routine that
doesn't have any business being vectorized and can't be inlined.

Signed-off-by: Palmer Dabbelt <palmer at dabbelt.com>
---
This probably can't actually manifest as a bug and it requires a bunch of
compiler version hunting, so I'm parking it for now.  If someone wants to pick
it up they're welcome to, otherwise I'll try and remeber to go dig around...
---
 arch/riscv/include/asm/vector.h      |  3 +++
 arch/riscv/kernel/traps_misaligned.c | 10 +---------
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index b61786d43c20..0264d37dc839 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -40,6 +40,8 @@
 	_res;								\
 })
 
+#define CLOBBER_V0 "v0"
+
 extern unsigned long riscv_v_vsize;
 int riscv_v_setup_vsize(void);
 bool insn_is_vector(u32 insn_buf);
@@ -423,6 +425,7 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
 #define riscv_v_thread_free(tsk)		do {} while (0)
 #define  riscv_v_setup_ctx_cache()		do {} while (0)
 #define riscv_v_thread_alloc(tsk)		do {} while (0)
+#define CLOBER_V0
 
 #endif /* CONFIG_RISCV_ISA_V */
 
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index f760e4fcc052..7e0f33523f0d 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -602,14 +602,6 @@ void check_vector_unaligned_access_emulated(struct work_struct *work __always_un
 	*mas_ptr = RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN;
 
 	kernel_vector_begin();
-	/*
-	 * In pre-13.0.0 versions of GCC, vector registers cannot appear in
-	 * the clobber list. This inline asm clobbers v0, but since we do not
-	 * currently build the kernel with V enabled, the v0 clobber arg is not
-	 * needed (as the compiler will not emit vector code itself). If the kernel
-	 * is changed to build with V enabled, the clobber arg will need to be
-	 * added here.
-	 */
 	__asm__ __volatile__ (
 		".balign 4\n\t"
 		".option push\n\t"
@@ -617,7 +609,7 @@ void check_vector_unaligned_access_emulated(struct work_struct *work __always_un
 		"       vsetivli zero, 1, e16, m1, ta, ma\n\t"	// Vectors of 16b
 		"       vle16.v v0, (%[ptr])\n\t"		// Load bytes
 		".option pop\n\t"
-		: : [ptr] "r" ((u8 *)&tmp_var + 1));
+		: : [ptr] "r" ((u8 *)&tmp_var + 1) : CLOBBER_V0 );
 	kernel_vector_end();
 }
 
-- 
2.39.5 (Apple Git-154)