[PATCH V2 2/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

[Drew Fustini]

On Sun, Jul 13, 2025 at 11:53:21AM -0400, guoren at kernel.org wrote:
> From: "Guo Ren (Alibaba DAMO Academy)" <guoren at kernel.org>
> 
> The early version of XuanTie C910 core has a store merge buffer
> delay problem. The store merge buffer could improve the store queue
> performance by merging multi-store requests, but when there are not
> continued store requests, the prior single store request would be
> waiting in the store queue for a long time. That would cause
> significant problems for communication between multi-cores. This
> problem was found on sg2042 & th1520 platforms with the qspinlock
> lock torture test.
> 
> So appending a fence w.o could immediately flush the store merge
> buffer and let other cores see the write result.
> 
> This will apply the WRITE_ONCE errata to handle the non-standard
> behavior via appending a fence w.o instruction for WRITE_ONCE().
> 
> This problem is only observed on the sg2042 hardware platform by
> running the lock_torture test program for half an hour. The problem
> was not found in the user space application, because interrupt can
> break the livelock.

The first paragraph states the problem was found on both the SG2042 and
TH1520, but this paragraph states it is only observed on the SG2042. Is
worth me trying to run lock_torture on the TH1520 for many hours?

Thanks,
Drew