[External] [PATCH] RISC-V: store percpu offset in CSR_SCRATCH

[yunhui cui]

Hi Radim,

On Wed, Jul 9, 2025 at 10:20 PM Radim Krčmář <rkrcmar at ventanamicro.com> wrote:
>
> 2025-07-09T19:42:26+08:00, yunhui cui <cuiyunhui at bytedance.com>:
> > Bench platform: Spacemit(R) X60
> > No changes:
> > 6.77, 6.791, 6.792, 6.826, 6.784, 6.839, 6.776, 6.733, 6.795, 6.763
> > Geometric mean: 6.786839305
> > Reusing the current scratch:
> > 7.085, 7.09, 7.021, 7.089, 7.068, 7.034, 7.06, 7.062, 7.065, 7.051
> > Geometric mean: 7.062466876
>
> Great results.
>
> > A degradation of approximately 4.06% is observed. The possible cause
> > of the degradation is that the CSR_TVEC register is set every time a
> > kernel/user exception occurs.
>
> I assume the same.
>
> > The following is the patch without percpu optimization, which only
> > tests the overhead of separating exceptions into kernel and user
> > modes.
>
> Is the overhead above with this patch?  And when we then use the
> CSR_SCRATCH for percpu, does it degrade even further?
>
> Thanks.


We can see that the percpu optimization is around 2.5% through the
method of fixing registers, and we can consider that the percpu
optimization can bring a 2.5% gain. Is there no need to add the percpu
optimization logic on the basis of the scratch patch for testing?

Reference: https://lists.riscv.org/g/tech-privileged/message/2485


Thanks,
Yunhui