[PATCH 3/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver

[Chen Wang]

On 8/28/2025 7:18 PM, ALOK TIWARI wrote:
>
>
> On 8/28/2025 7:47 AM, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang at outlook.com>
>>
[......]

>> +
>> +#include <linux/kernel.h>
>> +#include <linux/of.h>
>> +#include <linux/pci.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> +
>> +#include "pcie-cadence.h"
>> +
>> +/*
>> + * SG2042 only support 4-byte aligned access, so for the rootbus 
>> (i.e. to read
>
> support -> supports
Nice catch!
>
>> + * the Root Port itself, read32 is required. For non-rootbus (i.e. 
>> to read
>> + * the PCIe peripheral registers, supports 1/2/4 byte aligned 
>> access, so
>> + * directly using read should be fine.
>> + *
>> + * The same is true for write.
> [clip]
>> +static int sg2042_pcie_probe(struct platform_device *pdev)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct pci_host_bridge *bridge;
>> +    struct cdns_pcie *pcie;
>> +    struct cdns_pcie_rc *rc;
>> +    int ret;
>> +
>> +    pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
>> +    if (!pcie)
>> +        return -ENOMEM;
>> +
>> +    bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
>> +    if (!bridge) {
>> +        dev_err(dev, "Failed to alloc host bridge!\n");
>> +        return -ENOMEM;
>> +    }
>> +
>> +    bridge->ops = &sg2042_pcie_host_ops;
>> +
>> +    rc = pci_host_bridge_priv(bridge);
>> +    pcie = &rc->pcie;
> First, pcie is allocated and then reassigned to &rc->pcie,
> which makes the initial allocation effectively leaked and unnecessary.

My fault.

Thanks,

Chen

[......]

>
> Thanks,
> Alok